Patents by Inventor Consuelo N. Tangpuz
Consuelo N. Tangpuz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110095417Abstract: This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: Fairchild Semiconductor CorporationInventors: Jocel P. Gomez, Consuelo N. Tangpuz
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Patent number: 7842555Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.Type: GrantFiled: January 6, 2009Date of Patent: November 30, 2010Assignee: Fairchild Semiconductor CorporationInventors: Rajeev D. Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Patent number: 7682877Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.Type: GrantFiled: May 9, 2008Date of Patent: March 23, 2010Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Patent number: 7582956Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: GrantFiled: March 29, 2007Date of Patent: September 1, 2009Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo N. Tangpuz, Romel N. Manatad
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Publication number: 20090117690Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.Type: ApplicationFiled: January 6, 2009Publication date: May 7, 2009Inventors: Rajeev D. Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Patent number: 7501702Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.Type: GrantFiled: June 24, 2004Date of Patent: March 10, 2009Assignee: Fairchild Semiconductor CorporationInventors: Rajeev D. Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Patent number: 7439613Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.Type: GrantFiled: May 6, 2004Date of Patent: October 21, 2008Assignee: Fairchild Semicondcutor CorporationInventors: Rajeev Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Publication number: 20080213946Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.Type: ApplicationFiled: May 9, 2008Publication date: September 4, 2008Inventors: Rajeev Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Patent number: 7215011Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: GrantFiled: August 25, 2005Date of Patent: May 8, 2007Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo N. Tangpuz, Romel N. Manatad
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Patent number: 7154168Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: GrantFiled: November 5, 2003Date of Patent: December 26, 2006Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo N. Tangpuz, Romel N. Manatad
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Patent number: 6989588Abstract: A semiconductor device including a leadframe and a die coupled thereto. A drain pad is coupled to the drain region of the die in a body that substantially envelopes the leadframe and the die. The body includes a window defined therein. The body is placed around the leadframe and the die such that a surface of the drain pad opposite the die is exposed through the window.Type: GrantFiled: September 24, 2001Date of Patent: January 24, 2006Assignee: Fairchild Semiconductor CorporationInventors: Maria C. Y. Quinones, Consuelo N. Tangpuz
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Patent number: 6949410Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: GrantFiled: June 27, 2003Date of Patent: September 27, 2005Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo N. Tangpuz, Romel N. Manatad
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Patent number: 6943434Abstract: A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.Type: GrantFiled: October 2, 2003Date of Patent: September 13, 2005Assignee: Fairchild Semiconductor CorporationInventors: Consuelo N. Tangpuz, Romel N. Manatad, Margie T. Rios, Erwin Victor R. Cruz
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Publication number: 20040207052Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.Type: ApplicationFiled: May 6, 2004Publication date: October 21, 2004Inventors: Rajeev Joshi, Jonathan A. Noquil, Consuelo N. Tangpuz
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Publication number: 20040130009Abstract: A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.Type: ApplicationFiled: October 2, 2003Publication date: July 8, 2004Inventors: Consuelo N. Tangpuz, Romel N. Manatad, Margie T. Rios, Erwin Victor R. Cruz
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Patent number: 6720642Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: GrantFiled: December 16, 1999Date of Patent: April 13, 2004Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo N. Tangpuz, Romel N. Manatad
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Publication number: 20040056364Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: ApplicationFiled: June 27, 2003Publication date: March 25, 2004Applicant: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo N. Tangpuz, Romel N. Manatad
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Publication number: 20030052408Abstract: A semiconductor device including a leadframe and a die coupled thereto. A drain pad is coupled to the drain region of the die in a body that substantially envelopes the leadframe and the die. The body includes a window defined therein. The body is placed around the leadframe and the die such that a surface of the drain pad opposite the die is exposed through the window.Type: ApplicationFiled: September 24, 2001Publication date: March 20, 2003Applicant: Fairchild Semiconductor CorporationInventors: Maria C.Y. Quinones, Consuelo N. Tangpuz
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Patent number: 6423623Abstract: A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.Type: GrantFiled: August 27, 1998Date of Patent: July 23, 2002Assignee: Fairchild Semiconductor CorporationInventors: Izak Bencuya, Maria Christina B. Estacio, Steven P. Sapp, Consuelo N. Tangpuz, Gilmore S. Baje, Rey D. Maligro