Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: Decision modules are strategically located along with various modules to route signals from either a test pattern generator or the data link layer through the various modules for performing scrambling, encoding, and serializing procedures on the signals before transmission of the signals on a serial bus. Decision modules are strategically placed along with various modules to route signals to either a test pattern checker or the data link layer through the various modules for performing descrambling, decoding, and deserializing procedures on the signals after receiving the signals from a serial bus.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: Methods and structure are disclosed for analyzing different signaling pathways through a test signal selection hierarchy utilizing test patterns. One embodiment comprises an integrated circuit that includes a block of circuitry, a test signal generator, and a test signal selection hierarchy. The block of circuitry generates internal operational (TOP) signals for performing functions. The test signal generator generates test patterns that correspond with the IOP signals. The test signal selection hierarchy receives IOP signals and the test patterns, and selectively routes received signals to test pads. The test signal selection hierarchy routes the test patterns via signaling pathways through the test signal selection hierarchy to provide outputs signals on the test pads. The output signals are usable by an external test system to determine two or more of: a crosstalk, inter-symbol interference, a signal skew, and a threshold voltage for detecting bit transition on signaling pathways.

Abstract: Decision modules are strategically located along with various modules to route signals from either a test pattern generator or the data link layer through the various modules for performing scrambling, encoding, and serializing procedures on the signals before transmission of the signals on a serial bus. Decision modules are strategically placed along with various modules to route signals to either a test pattern checker or the data link layer through the various modules for performing descrambling, decoding, and deserializing procedures on the signals after receiving the signals from a serial bus.

Abstract: The different illustrative embodiments provide a method and apparatus for managing peak detector circuits. A first number of voltages for a first number of signals detected by a peak detector circuit connected to a wire in a bus system is identified. The first number of signals is used to send data over the wire. The first number of voltages is for a first number of transmission speeds for the first number of signals. A second number of voltages for a second number of signals detected by the peak detector circuit is identified. The second number of signals is present in the wire in an absence of the data being sent over the wire. The second number of voltages is for a second number of transmission speeds for the second number of signals. A number of settings are selected for the peak detector circuit based on the first number of voltages and the second number of voltages.

Abstract: Methods and apparatus for interconnecting Serial Attached SCSI (SAS) or Serial Advanced Technology Attachment (SATA) devices using either an electrical communication medium or an optical communication medium. Each device includes an out of band (OOB) encoder/decoder (endec) logic component to translate between standard OOB signals used by the devices and digitally encoded OOB signals exchanged over the communication medium. Thus the devices may be coupled using either optical or electrical cabling. The digitally encoded OOB signals may also be scrambled to reduce electromagnetic interference (EMI) generated during OOB communications using the digitally encoded OOB signals. The scrambled digitally encoded OOB signals may comprise information regarding capabilities of the device that generated the underlying OOB signal. Such information may indicate to the other high speed device certain capabilities of the transmitting device—the information to be used in establishing logical connections between devices.

Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.

Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.

Abstract: In an integrated circuit, test signals are routed from test points through a hierarchy of distributed multiplexers to output pads. The multiplexers are distributed locally to various regions that are arranged in a hierarchy of regional levels. Thus, each test signal is routed to the locally distributed multiplexer, and only a portion of the test signals reach the top-level multiplexer.

Abstract: A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell. The description of the functionally extraneous cell is altered so that the layout tool produces a second layout of the die that functionally couples the first and second functionally extraneous cells without altering the position of the second functionally extraneous cell with respect to a logically functional cell. The description of the functionally extraneous cell complies with the description constraints for cells.

Abstract: An integrated circuit device with reduced noise is described. In traditional simultaneous output switching integrated circuits the noise is proportional to the number of concurrently switching outputs. This excessive supply noise can cause the integrated circuit to malfunction through the loss of data. In the present invention, switching supply noise is reduced in the device without increasing the number of input-output pins by synchronously skewing the output driver. In a preferred embodiment, flip-flops are used to control the phase of the switching outputs in order to reduce the noise and instantaneous power by the number of phase assignments.

Abstract: A precision delay circuit having two delay chains to provide equal delay periods is described. A rising edge of an input pulse signal is supplied to the first delay chain and the falling edge is supplied to the second delay chain. The resultant output signal maintains the pulse width of the input signal and pulse distortion is minimized. In another aspect, a delay circuit for generating a delayed assertion signal that does not maintain the width of the original input signal pulse and which is substantially immune to noise problems is described. An assertion edge of a resultant pulse is timed by the incoming pulse, but the de-assertion edge is timed by the delayed de-assertion edge of the incoming pulse.