Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Abstract: According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.

Abstract: Methods, system, and computer programs for compensating for introducing data dependent jitter into a test signal using a testing instrument are disclosed. The method includes generating a test pattern that comprises a plurality of intervals. Each of the intervals includes a number of redundant samples that correspond to a sample in a test source pattern. The test pattern is digitally modified to generate a modified test pattern that includes data dependent jitter.

Abstract: Methods, system, and computer programs for compensating for introducing data dependent jitter into a test signal using a testing instrument are disclosed. The method includes generating a test pattern that comprises a plurality of intervals. Each of the intervals includes a number of redundant samples that correspond to a sample in a test source pattern. The test pattern is digitally modified to generate a modified test pattern that includes data dependent jitter.

Abstract: A storage device includes a storage medium and a probe having a tip and a first magnetic element. The tip of the probe is adapted to form a dent in the storage medium. The storage device further has a second magnetic element, where the first and second magnetic elements are adapted to interact magnetically to indicate a storage state.

Abstract: A method for determining memory element values may include: selecting a column of interest containing a desired memory element, disabling the desired memory element, measuring a first current provided to the column of interest, adjusting measurement circuitry to compensate for skew introduced by undesired memory elements, enabling the desired memory element, and measuring a second current provided to the column of interest.

Abstract: A method of performing a read operation from a first magnetic random access memory (MRAM) cell in a memory cell string that includes the first MRAM cell coupled to a second MRAM cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first MRAM cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second MRAM cells in response to applying a write sense current to the first MRAM cell.

Abstract: A storage device includes a probe having a tip, the tip comprising a first portion and a second portion. The storage device also includes a storage medium having a surface, where the tip of the probe is adapted to form a dent in the storage medium. The second portion of the tip is electrically contacted to the surface of the storage medium in response to the tip being engaged in the dent, and the second portion of the tip is spaced apart from the surface of the storage medium in response to the first portion being engaged on the surface of the storage medium and not engaged in the dent.

Abstract: A storage device includes a probe, and a substrate comprising a storage medium and heating elements. The heating elements area adapted to heat respective regions of the storage medium to form perturbations in the respective regions of the storage medium, and the probe is adapted to detect the perturbations.

Abstract: A storage device includes a storage medium and a probe having a tip and a first plate. The tip of the probe is adapted to form a dent in the storage medium to represent a state of a data bit. The storage device also includes a second plate, where the first plate and second plate cooperate to form a variable capacitance that varies between different capacitance values depending on whether the tip of the probe is engaged in the dent.

Abstract: A storage device includes a probe having plural tips, and a storage medium having a surface. At least a first one of the tips is adapted to form a dent in the storage medium, and at least a second one of the tips is adapted to be electrically contact the surface of the storage medium in response to the first tip being engaged in the dent. The second tip is electrically isolated from the storage medium in response to the first tip being engaged on the surface of the storage medium and not being engaged in the dent.

Abstract: A storage device includes plural groups of memory cells, wherein the memory cells comprise magnetoresistive elements. Each group includes a transistor, and the memory cells of each group include a first set of parallel connected memory cells that are connected to a node of the transistor. The storage device further includes a sensing device to detect a state of a memory cell in a selected one of the groups.

Abstract: A storage device includes an electrically conductive storage medium and a probe having a tip that is electrically conductive. The tip is electrically contacted to the storage medium and is adapted to form a dent in the storage medium. The tip is also adapted to cooperate with the storage medium to provide a variable resistance based on whether the tip is engaged in the dent.

Abstract: A method of performing a read operation from a first magnetic random access memory (MRAM) cell in a memory cell string that includes the first MRAM cell coupled to a second MRAM cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first MRAM cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second MRAM cells in response to applying a write sense current to the first MRAM cell.

Abstract: A method for determining memory element values may include: selecting a column of interest containing a desired memory element, disabling the desired memory element, measuring a first current provided to the column of interest, adjusting measurement circuitry to compensate for skew introduced by undesired memory elements, enabling the desired memory elements, and measuring a second current provided to the column of interest.

Abstract: A data storage device comprising a first memory cell string that includes at least a first magnetic random access memory (MRAM) cell coupled to a second MRAM cell and a circuit coupled to a node between the first MRAM cell and the second MRAM cell is provided. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and in response to a write sense current being applied across the first MRAM cell.

Abstract: A method for performing a read operation from a magnetic random access memory (MRAM) cell in a memory cell string is provided. The method includes applying a constant current through the memory cell string, measuring a first voltage across the memory cell string, applying a write sense current across the MRAM cell, measuring a second voltage across the memory cell string, and determining whether the first voltage differs from the second voltage.