Abstract: An integrated circuit chip (110) adapted to provide interconnect capability and an AC interconnect test method therefor. Test and control data are scanned in the scan-path of latches (114 and 115) to initialize the AC interconnect test. Subsequently the functional system mode is simulated by applying the functional-system clocks via lines (118 and 128).

Abstract: A test pattern generator includes a random pattern generator and a shift register. The random pattern generator generates a series of digits which are input to the shift register and stored therein. Each digit output by the random pattern generator has a probability of having a first value, such as representing "1". The output probability of the random pattern generator is adjustable. The shift register has a plurality of outputs for outputting a test pattern comprising the stored digits. The shift register includes a series of latches and at least a first logic circuit connecting the output of the random pattern generator to the input of a first latch, or connecting the output of a latch to the input of a next adjacent latch. In a first state, the logic circuit has an output probability which is independent of the output probability of the random pattern generator. In a second state, the logic circuit has an output probability which is dependent on the output probability of the random pattern generator.

Abstract: An integrated circuit chip with built-in self-test for logic fault detection is described which comprises a number of combinational logic circuits and a number of shift register latches. The combinational logic circuits are coupled via the shift register latches and the shift register latches are connected to form test scan paths. Test weights are created and combined with test patterns and are then applied to the test scan paths of the integrated circuit chip. In contrast to the prior art where the test weights are taken out of a weight storage table, the invention generates the test weights with the help of a so-called "finite state machine", i.e. with a circuit which creates a finite number of test weights without storing them. Therefore, no weight storage table or the like is necessary and the whole tester can be incorporated on the chip.