Abstract: Apparatus and methods for ultrasound probes are provided. In certain implementations, a receive switch for an ultrasound probe includes a first field effect transistor (FET) and a second FET electrically connected in series between a first terminal and a second terminal with the FETs' sources connected to one another. The receive switch includes a positive threshold detection and control circuit for turning off the receive switch when a voltage of the first terminal is greater than a positive threshold voltage, and a negative threshold detection and control circuit for turning off the receive switch when the first terminal's voltage is less than a negative threshold voltage. The receive switch further includes a gate bias circuit that can bias the gates of the first and second FETs so as to turn on the receive switch when no positive or negative high voltage conditions are detected on the first terminal.

Abstract: A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.

Abstract: Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit.

Abstract: Apparatus and methods for ultrasound probes are provided. In certain implementations, a receive switch for an ultrasound probe includes a first field effect transistor (FET) and a second FET electrically connected in series between a first terminal and a second terminal with the FETs' sources connected to one another. The receive switch includes a positive threshold detection and control circuit for turning off the receive switch when a voltage of the first terminal is greater than a positive threshold voltage, and a negative threshold detection and control circuit for turning off the receive switch when the first terminal's voltage is less than a negative threshold voltage. The receive switch further includes a gate bias circuit that can bias the gates of the first and second FETs so as to turn on the receive switch when no positive or negative high voltage conditions are detected on the first terminal.

Abstract: Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit.

Abstract: A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.

Abstract: A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.

Abstract: A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.

Abstract: A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.

Abstract: An integrated circuit adapted for use in a data path of a disk storage system of a type wherein data is recorded at different rates depending upon the storage track of the data and includes servo bursts of head positioning signals disbursed throughout the data on all of the tracks. The circuit includes a variable cut off low pass filter that is adjusted both for the rate of data being read and for the rate of the servo bursts when being read. An automatic gain control and a pulse detector are similarly dynamically adjusted in characteristics to fit that of the data and servo bursts when each is being read from the disk. An output of the filter provides both read data and head positioning signals. A write data path is also provided as part of the circuit.

Abstract: A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock.

Abstract: A single integrated circuit chip provides an interface to both magneto-resistive read elements and inductive write elements of a plurality of read/write heads of a disk drive mass data storage system. Separate multiplexers and current sources are used for the read and write channels. The read element of a head selected by one of the multiplexers is preamplified on the chip. A write driver circuit is also provided, being connected to a write element of a head selected by the other of the multiplexers.

Abstract: A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.

Abstract: A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock. The phase locked loop includes a phase detector responsive to the reference clock and the reference biquad, whose output is integrated.

Abstract: A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock.

Abstract: A constant loop gain phase lock loop for recovering a clock from non-uniformly spaced data pulses utilizes a programmable current source and charge pump whereby the current into the charge pump is proportional to the number of VCO clock periods between data pulses. As the time between pulses increases the current charging the pump increases and when the time between pulses decreases the current charging the pump decreases to maintain a constant loop gain independent of the data pattern.

Abstract: A preamplifer for use with a magneto-resistive playback head in which a d.c. current source provides current through a field effect transistor and the magneto-resistive element to ground. An operational transconductance amplifier included in a feedback loop provides a bias voltage for the field-effect transistor, whereby the voltage across the said magneto-resistive element is held constant while the resistance of said element changes. The resulting a.c. current flowing through the magneto-resistive element flows only through the feedback loop and an output resistor connected across the inputs of the operational transconductance amplifier. The amplification of the circuit is approximately the resistance of the output resistor divided by the resistance of the magneto-resistive element.