Patents by Inventor Corey Gee

Corey Gee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single instruction multiple data add processors, methods, systems, and instructions
    Patent number: 9804841
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl A. Alberola
  • SINGLE INSTRUCTION MULTIPLE DATA ADD PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    Publication number: 20150134936
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventors: Corey GEE, Bapiraju VINNAKOTA, Saleem MOHAMMADALI, Carl A. ALBEROLA
  • Data packet arithmetic logic devices and methods
    Patent number: 8938607
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl A. Alberola
  • DATA PACKET ARITHMETIC LOGIC DEVICES AND MEHTODS
    Publication number: 20130290684
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl A. Alberola
  • Data packet arithmetic logic devices and methods
    Patent number: 8473719
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl A. Alberola
  • Circuit to extract nonadjacent bits from data packets
    Patent number: 7353371
    Abstract: A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. In an ESET function, data fields in respective source packets are copied to adjacent data fields in a result packet governed by a field locator packet. In an EXTRACT function, data fields in a source packet are copied to adjacent data fields in a result packet governed by a field locator packet. In a SCATTER function, adjacent data fields in a source packet are copied to data fields in respective result packets governed by a field locator packet.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Corey Gee, Bapi Vinnakota
  • Data packet arithmetic logic devices and methods
    Publication number: 20070074002
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Application
    Filed: October 31, 2006
    Publication date: March 29, 2007
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl Alberola
  • Data packet arithmetic logic devices and methods
    Patent number: 7139900
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl A. Alberola
  • Asynchronous communication protocol using efficient data transfer formats
    Patent number: 6889267
    Abstract: An embodiment of the present invention includes first and second storage elements. The first storage element stores request information transmitted from a first processor operating at a first frequency. The first and second processors operate at different frequencies. The request information is organized according to a request format. The second storage element stores response information transmitted by a second processor operating at a second frequency different than the first frequency in response to the request information. The response information is organized according to a response format.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 3, 2005
    Assignee: Intel Corporation
    Inventors: Nicholas Duresky, Sameer Nanavati, Sunil Chaudhari, Corey Gee
  • Data packet arithmetic logic devices and methods
    Publication number: 20040260914
    Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 23, 2004
    Inventors: Corey Gee, Bapiraju Vinnakota, Saleem Mohammadali, Carl A. Alberola
  • Circuit to extract logical values at arbitrary bit positions
    Publication number: 20040109444
    Abstract: A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. In an ESET function, data fields in respective source packets are copied to adjacent data fields in a result packet governed by a field locator packet. In an EXTRACT function, data fields in a source packet are copied to adjacent data fields in a result packet governed by a field locator packet. In a SCATTER function, adjacent data fields in a source packet are copied to data fields in respective result packets governed by a field locator packet.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 10, 2004
    Inventors: Corey Gee, Bapi Vinnakota
  • Asynchronous communication protocol using efficient data transfer formats
    Publication number: 20040103224
    Abstract: An embodiment of the present invention includes first and second storage elements. The first storage element stores request information transmitted from a first processor operating at a first frequency. The first and second processors operate at different frequencies. The request information is organized according to a request format. The second storage element stores response information transmitted by a second processor operating at a second frequency different than the first frequency in response to the request information. The response information is organized according to a response format.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 27, 2004
    Inventors: Nicholas Duresky, Sameer Nanavati, Sunil Chaudhari, Corey Gee