Patents by Inventor Corey Joiner

Corey Joiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260190459
    Abstract: Integrated circuit (IC) devices having dielectric material separating adjacent source and drain bodies. An IC device may include adjacent first and second transistor structures having adjacent source or drain bodies separated by a dielectric material on first and second sidewalls of a first of the source or drain bodies (but only on the sidewall of the second source or drain body adjacent the first source or drain body). An isolation structure of a second dielectric material may be on the first dielectric material, on the first and second source or drain bodies, and between first and second contact structures on the first and second source or drain bodies. The dielectric material on first and second sidewalls of the first source or drain body may be selectively deposited (e.g., conformally) before the second source or drain body is grown.
    Type: Application
    Filed: December 26, 2024
    Publication date: July 2, 2026
    Applicant: Intel Corporation
    Inventors: Sudipto Naskar, Seung Hoon Sung, Sean Pursel, Wen-Hsi Huang, Mithun Ghosh, Corey Joiner, Chun-Kuo Huang, Minwoo Jung, Jessica Panella
  • Publication number: 20260059801
    Abstract: Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.
    Type: Application
    Filed: August 26, 2024
    Publication date: February 26, 2026
    Applicant: Intel Corporation
    Inventors: Xia Li, Sudipto Naskar, Chun-Kuo Huang, Corey Joiner, Wen-Hsi Huang
  • Publication number: 20250212464
    Abstract: Described herein are nanoribbon transistors with bilayer cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a first, inner layer next to the gate stack, and a second, outer layer next to the source or drain. The inner layer may be a low-k dielectric material, while the outer layer may be a high-k dielectric material.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Intel Corporation
    Inventors: Sudipto Naskar, Shao Ming Koh, Chun Kuo Huang, Corey Joiner