Abstract: The present disclosure relates to sensor systems for electronic ophthalmic devices. In certain embodiments, the sensor systems may comprise a sensor such as an adjustable resistor configured in series with an eye of a user of the electronic ophthalmic device. The sensor systems may comprise a gain stage configured to amplify a signal indicative of a difference between a voltage drop across the eye and the adjustable resistor. The sensor systems may comprise an integrator configured to integrate the amplified signal. A resistance value of the adjustable resistor is configured to cancel a DC component of a resistance of the eye when an electrical current is caused to flow through the eye and the adjustable resistor. As such, the configured resistance value of the adjustable resistor is indicative of an impedance of the eye.

Abstract: The present disclosure relates to sensor systems for electronic ophthalmic devices. In certain embodiments, the sensor systems may comprise a sensor such as an adjustable resistor configured in series with an eye of a user of the electronic ophthalmic device. The sensor systems may comprise a gain stage configured to amplify a signal indicative of a difference between a voltage drop across the eye and the adjustable resistor. The sensor systems may comprise an integrator configured to integrate the amplified signal. A resistance value of the adjustable resistor is configured to cancel a DC component of a resistance of the eye when an electrical current is caused to flow through the eye and the adjustable resistor. As such, the configured resistance value of the adjustable resistor is indicative of an impedance of the eye.

Abstract: The present disclosure relates to sensor systems for electronic ophthalmic devices. In certain embodiments, the sensor systems may comprise a first electrode configured to be selectively overlaid by one or more of an upper eyelid and a lower eyelid of a user, a second electrode configured to be selectively overlaid by one or more of an upper eyelid and a lower eyelid of a user, and a system controller cooperatively associated with the first electrode and the second electrode to receive a capacitance measurement therefrom, the system controller configured to determine a position of one or more of the upper eyelid and the lower eyelid in spatial coordinates based on the capacitance measurement received from the first electrode and the second electrode.

Abstract: An anti-aliasing photodetector system for a powered ophthalmic device, such as a contact lens, may be utilized for any number of functions. The anti-aliasing photodetector system converts current from an array of photodetectors into a voltage for use in other aspects of the powered ophthalmic device. The anti-aliasing photodetector system comprises a photodiode array including a plurality of individual photodiodes, an integrate-and-hold circuit, including a capacitor and switch to convert current to voltage, and an analog-to-digital converter. The anti-aliasing photodetector system provides for low power consumption, a wide dynamic range, noise rejection, and is capable of detecting incident ambient visible light as well as incident infrared light.

Abstract: An anti-aliasing photodetector system for a powered ophthalmic device, such as a contact lens, may be utilized for any number of functions. The anti-aliasing photodetector system converts current from an array of photodetectors into a voltage for use in other aspects of the powered ophthalmic device. The anti-aliasing photodetector system comprises a photodiode array including a plurality of individual photodiodes, an integrate-and-hold circuit, including a capacitor and switch to convert current to voltage, and an analog-to-digital converter. The anti-aliasing photodetector system provides for low power consumption, a wide dynamic range, noise rejection, and is capable of detecting incident ambient visible light as well as incident infrared light.

Abstract: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.