Abstract: In the fabrication of EDRAM/SDRAM silicon chips with ground rules beyond 0.18 microns, a Si3N4 barrier layer is deposited onto the patterned structure during the borderless polysilicon contact fabrication. It is required that this layer be conformal and has a high hydrogen atom content to prevent junction leakage. These objectives are met with the method of the present invention. In a first embodiment, the Si3N4 layer is deposited in a Rapid Thermal Chemical Vapor Deposition (RTCVD) reactor using a NH3/SiH4 chemistry at a temperature and a pressure in the 600-950° C. and 50-200 Torr ranges respectively. In a second embodiment, it is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace using a NH3/SiH2Cl2 chemistry (preferred ratio 1:1) at a temperature and a pressure in the 640-700° C. and 0.2-0.8 Torr ranges respectively.

Abstract: A multilayered quantum conducting barrier (MQCB) structure formed on two semiconductor regions having a different crystalline nature and a thin layer of an insulating material sandwiched between said semiconductor regions. An undoped amorphous silicon layer continuously coats these two semiconductor regions and insulating layer. The surface of the undoped amorphous silicon layer is nitridized to produce a superficial film of a nitride based material to form the desired quantum conducting barrier (QCB). A stack consisting of at least one dual layer comprised of a bottom undoped amorphous silicon layer and a top dopant monolayer is formed on said undoped amorphous silicon layer. After thermal processing, the MQCB structure operates as a strap allowing an electrical continuity between these semiconductor regions through the QCB by a quantum mechanical effect.

Abstract: Improved reliability structures containing quantum conductive barrier layer structures are obtained by employing quantum conductive layers in combination with thin regions of amorphous or microcrystalline semiconductor material. The quantum conductive structures are especially useful when incorporated into trench capacitors to reduce or eliminate the occurrence of low temperature fails and single cell fails in DRAM circuits.