Patents by Inventor Cormac Michael O'Connell
Cormac Michael O'Connell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079257Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.Type: ApplicationFiled: April 26, 2023Publication date: March 7, 2024Inventors: Shih-Lien Linus LU, Cormac Michael O'CONNELL
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Publication number: 20240069794Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
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Patent number: 11847345Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.Type: GrantFiled: June 28, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
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Publication number: 20230388135Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Shih-Lien Linus LU, Cormac Michael O'Connell
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Patent number: 11811953Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.Type: GrantFiled: November 30, 2020Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
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Patent number: 11676658Abstract: An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled.Type: GrantFiled: August 23, 2021Date of Patent: June 13, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Cormac Michael O'Connell
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Patent number: 11664258Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.Type: GrantFiled: June 4, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
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Publication number: 20220326875Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Inventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
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Patent number: 11403033Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.Type: GrantFiled: November 6, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
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Patent number: 11258596Abstract: A method for utilizing a plurality of physical unclonable function (PUF) cells to generate a signature key with a desired bit length is provided. The method includes setting a state of each of the plurality of PUF cells to a uniform level; obtaining an order of change in the state of at least a portion of the plurality of PUF cells; and generating the signature key at least based on the order.Type: GrantFiled: August 13, 2018Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
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Publication number: 20210383860Abstract: An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventor: Cormac Michael O'Connell
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Publication number: 20210296151Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
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Patent number: 11100980Abstract: An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled.Type: GrantFiled: September 26, 2019Date of Patent: August 24, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Cormac Michael O'Connell
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Publication number: 20210250191Abstract: Disclosed is a physical unclonable function generator circuit and method.Type: ApplicationFiled: April 27, 2021Publication date: August 12, 2021Inventor: Cormac Michael O'Connell
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Publication number: 20210200462Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.Type: ApplicationFiled: November 6, 2020Publication date: July 1, 2021Inventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
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Patent number: 11043404Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.Type: GrantFiled: April 27, 2018Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
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Patent number: 11005669Abstract: Disclosed is a physical unclonable function generator circuit and method.Type: GrantFiled: September 7, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Cormac Michael O'Connell
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Patent number: 10958270Abstract: A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line.Type: GrantFiled: October 13, 2019Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell, Kun-Hsi Li
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Publication number: 20210083887Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Shih-Lien Linus LU, Cormac Michael O'CONNELL
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Patent number: 10880102Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.Type: GrantFiled: September 21, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell