Abstract: This invention relates to a process for producing cyanoacetates involving contacting a salt of an alkyl, alkenyl, alkynyl or aryl formyl acetate with a hydroxyl amine acid under appropriate conditions and for a time sufficient to yield a cyanoacetate.

Abstract: A receiver can include a first set of one or more amplifier stages configured to amplify input signals in a plurality of communication bands. The receiver can further include a second and third set of one or more amplifier stages. The second set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a first one of the plurality of communication bands. Alternatively, the third set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a second one of the plurality of communication bands.

Abstract: A receiver can include a first set of one or more amplifier stages configured to amplify input signals in a plurality of communication bands. The receiver can further include a second and third set of one or more amplifier stages. The second set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a first one of the plurality of communication bands. Alternatively, the third set of one or more amplifier stages can be configured to selectively receive the input signals in the plurality of communication bands amplified by the first set of one or more amplifier stages and to amplify one or more input signals in a second one of the plurality of communication bands.

Abstract: A pulse signal compensation circuit of a pulse generator can include a pulse measurement circuit and a compensation generator circuit. The pulse measurement circuit can be configured to receive a plurality of pulse signals and to generate an average duty cycle or pulse overlap signal proportional to the duty cycle or pulse overlap of the plurality of pulses. The compensation generator circuit can be configured to receive the average duty cycle or pulse overlap signal and generate a duty cycle or pulse overlap compensation signal based on the average duty cycle or pulse overlap signal. The compensation signal can be utilized to adjust the duty cycle, amount of positive or negative pulse width overlap, and or the like of the plurality of pulse signals.

Abstract: A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former. The plurality of antennas can be arranged in an array. The plurality of compound analog-to-digital converters can include respective inputs coupled to respective ones of the plurality of antennas. Respective output of the plurality of compound analog-to-digital converters can be coupled to the beam former. Each compound analog-to-digital converter can include a plurality of time interleaved sub-analog-to-digital converters. Sampling by the sub-analog-to-digital converters can be random between the sub-analog-to-digital converters within respective compound analog-to-digital converters and random between the plurality of compound analog-to-digital converters. In addition, dynamic element mismatch using a random bitstream generator can be employed in digital-to-analog converters and analog-to-digital converters.

Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.