Patents by Inventor Cornelia H. Blanton

Cornelia H. Blanton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5256582
    Abstract: The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: October 26, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Dan M. Mosher, Cornelia H. Blanton, Joe R. Trogolo, Larry Latham, David R. Cotton, Bob Todd
  • Patent number: 5181095
    Abstract: An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.
    Type: Grant
    Filed: April 19, 1991
    Date of Patent: January 19, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Dan M. Mosher, Larry Latham, Bob Todd, Cornelia H. Blanton, Joe R. Trogolo, David R. Cotton
  • Patent number: 5153697
    Abstract: An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.
    Type: Grant
    Filed: May 6, 1991
    Date of Patent: October 6, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Dan M. Mosher, Cornelia H. Blanton, Joe R. Trogolo, Larry Latham, David R. Cotton
  • Patent number: 5034337
    Abstract: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.
    Type: Grant
    Filed: August 29, 1990
    Date of Patent: July 23, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Dan M. Mosher, Cornelia H. Blanton, Joe R. Trogolo, Larry Latham, David R. Cotton