Abstract: In a video-processing unit comprising a processing means, memory means and a memory manager, an output of the processing means is coupled to the memory manager for storing of the processed data from the processing means in the memory means to allow execution of different processes in video-processing unit by a single processing means.

Abstract: The invention relates to a sampler (2) and a method for converting a signal (S1) into a multiple signal (S220 . . . S222), comprising a stage (22) of sample & hold circuits (220 . . . 222). The sampler (2) comprises an input circuit (20) having means (201) for applying a signal (S1) in bursts (S20) to the stage (22). Successive bursts are separated by a time interval (&Dgr;t1, &Dgr;t2). In this way, an increased sample time of the signal (S222) in the last channel is provided for a display panel (3) or a subsequent sample & hold circuit. In general, use of the invention ensures that the number of stages in a sampler can be reduced. The resulting, more compact design is very suitable for integration because the power consumption can be kept low. The arrangement requires less buffering, which makes it simpler to avoid uniformity problems and ghost images. A signal input in bursts requires memories.

Abstract: In a video-processing unit comprising a processing means, memory means and a memory manager, the processing means comprises an N-tap digital filter for performing scaling operations on a sampled image present in the memory means. The N-tap digital filter further comprises a predetermined first number of line memories. Each line memory is arranged to contain a predetermined second number of samples of selected lines of the sampled image in the memory means. The second number of samples is smaller than the total number of samples of each line of the sampled image.

Abstract: In a memory arrangement including a frame buffer unit (FB) having memory equipment (SDRAM) clocked by a memory clock (fm), and a scaler unit (S), the scaler unit (S) has at least one line memory (inplinmem, outplinmem) for converting a continuous input data stream into a frame buffer data stream in which samples of two successive data bursts of N samples are situated N+&Dgr;N samples apart from each other, and/or for converting such a frame buffer data stream into a continuous output data stream, to allow the frame buffer unit (FB) to operate with less than three different clocks.

Abstract: In a plasma-addressed display device according to the invention, a group (G) of three pixels (16) is constituted out of one common data electrode (18) and a group of plasma channels (20). The colour filters are aligned with the plasma channels (20) of the group. In this way the number of data electrodes (18) and thus the number of connections thereto reduces by a factor equal to the number of pixels (16) in a group (G). The number of plasma channels (20) increases with the same factor, but the total number of connections decreases as the number of rows is lower than the number of groups (G) of pixels (16).

Abstract: A known plasma-addressed electro-optical color display device comprises groups (G) of three pixels (16), each group (G) is constituted out of one common plasma channel (20) and a three data electrodes (18). Color filters are aligned with the data electrodes. The number of plasma channels being lower than the number of groups of data electrodes.

Abstract: A timing circuit which is used to synchronize different circuit to each other. The timing circuit includes adjustable delay apparatus which delay an input signal with a predetermined value. The timing circuit uses counting devices to count the input signal and the delayed output signal and thereby provides a simple and more cost effective timing circuit.