Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.

Abstract: A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.

Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A) are provided for addressing said memory (EM) so as to operate said register memory sections as shift registers and to map shift register accesses of the at least one access port (P1 to PZ) to predetermined addresses in the global address space of the memory (EM). In this way, it is possible to combine a plurality of FIFO memories in a single addressable memory device. This implementation is favourable in view of power consumption and area. Furthermore, by introducing a buffer memory, a multi-port memory device can be replaced by a single-port memory device of the same capacity. This advanced implementation also provides a reduced cycle and access time.

Abstract: An electronic device is provided which comprises a plurality of processing units (IP1-IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IP1-IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word-asynchronous communication.

Abstract: The state transition of a linear feedback shift register (LFSR) controlled by a clock (310) with length N and step size W, W being at least two, is accomplished via a next-state function (320). The next-state function deploys a state transition matrix (350). The state vector (330), which represents the contents of the LFSR, is either multiplied sequentially by the state transition matrix or multiplied by the state transition matrix to the power of W (multiple state transition matrix). The method and the LFSR according to the invention are characterized in that the multiple state transition matrix is decomposed in a first matrix (360) and a second matrix (370), the first matrix comprising at most N+W+1 different expressions and the second matrix comprising at most N+W+1 different expressions. The LFSR further comprises means to multiply the state vector by the second matrix and the first matrix, and means for computing the first matrix.

Abstract: To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.

Abstract: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Abstract: An apparatus includes at least a first hardware part (AP1) and a second hardware part (AP2). Each of the first and second part include a respective processing element (CPU-1, CPU-2) and a respective signal connection to a respective memory element (MEM-1, MEM-2) for providing program code to the processing element of the respective part. The apparatus further includes a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data. A fourth hardware part of the apparatus includes an I/O network (AP-4) for enabling communication between elements of the first and third part under control of first configuration data and for enabling communication between elements of the second and third part under control of distinct second configuration data.

Abstract: A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The first data size is equal to or smaller than the size of memory port. The processing system including at least one data register (514) of the first data size connected to the memory port (505), and at least one data port (525) of the second data size connected to the data register (525) and the processor for enabling access to data elements of the second size.

Abstract: A location system including a base station (120, 200) and a responder tag (140, 250) that communicate using an acoustic signal to determine the location of the tag in a bounded 3D space (100). The base station transmits a request signal (310) encoded with the identifier of a particular tag. The particular tag responds after a fixed delay (t2?t1) with an acoustic response signal (330). The base station determines the location of the tag based on the received line of sight signal (330) and its reflections (340). The response signal may be encoded with data indicating a status of the tag, or data from associated sensors (270) or actuators (280). The request signal may also be encoded with data for controlling the tag or the associated sensors and actuators. A power management scheme may be carried out by the tag.

Abstract: A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.

Abstract: Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators which generate basic codes in vector format. However, a disadvantage of such a configurable vector processor is that it cannot provide a composite code which is dependent on such basic codes. This is necessary if the configurable vector processors should be flexible enough to support a variety of CDMA-like standards. The device according to the invention is provided with at least two weighted sum units, which are able to make a selection out of a plurality of incoming basic-code vectors by means of a weighted sum operation, under the control of a configuration word.

Abstract: A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).