Abstract: For transient-current testing of an electronic circuit, a differentiating current measuring device is arranged for measuring an undershoot voltage for each of a series of current pulses controlled in the circuit. In particular, the device is executed in integrated circuit technology and simulates a differentiating current probe. Furthermore, it may have calibration for imparting an offset voltage to each undershoot voltage of the series. This calibrates an actual potential of the simulation and produces for a correct Device Under Test in each cycle a substantially uniform undershoot voltage.

Abstract: A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip is used to make a notch in a vertical interconnect area of two organic electrically conducting areas separated from each other by an organic electrically insulating area. The method is used in the manufacture of integrated circuits consisting substantially of organic materials.

Abstract: An identification transponder comprising an identification code generator (10) embodied as an integrated circuit predominantly comprising organic materials. The integrated circuit may be provided on an anti-theft sticker (5) accommodating an LC resonant circuit (3, 4).

Abstract: A device compensated for an undesired capacitance includes a first and a second node between which nodes the undesired capacitance is present. A diode driven in breakthrough is coupled between the first and the second node. As a diode driven in breakthrough exhibits the characteristics of a negative capacitance, a compensation of the undesired capacitance is achieved.

Abstract: The invention relates to a semiconductor memory with a semiconductor body which is provided at a surface with a system of memory elements arranged in rows and columns. For addressing, the surface is provided with a system of mutually adjacent parallel selection lines 4, each coupled at one end to a selection transistor 19 with which the connection between the selection line and peripheral electronics can be opened or closed. These transistors are thin-film transistors which are formed, for example, in the selection lines themselves. As a result of this, the selection lines, and thus also the memory elements in the matrix, can be provided with minimum pitch.

Abstract: Latch circuit including a differential amplifier T1, T2 for amplifying a data signal D, ND to be latched, applied to the inputs 1, 2 of the differential amplifier, a flip-flop T3, T7, T4, T8 for latching the amplified data signal across the load impedances 6, 7 which are connected to the transistors T1, T2 through switching transistors T5 and T6 if the clock signal CLK is high and are disconnected therefrom if the clock signal is low. When there is a high clock signal the emitter junctions 11, 14 of the flip-flop are currentless. The transistors T5 and T6 fix the voltage at these junctions, and thereby avoid a variation of the junction voltage. Consequently, the decision accuracy of the latching operation is retained even with high clock signal frequencies.

Abstract: 1-Bit signma-delta modulator having a loop filter (5,6,8), a first negative feedback loop (13,7,8) and a second negative feedback loop (14,4,5,6,8). The filter sections 5 and 8 are passive filter elements and filter section 6 is a high-gain active filter element. A circuit of this type makes a very high clock rate possible in the decision switch 10.

Abstract: An electroscopic fluid picture-display device suitable for display television images and operating with pulse duration modulation. A picture signal sample-and-hold circuit (S/H) is followed by a pulse duration modulator (UG, DE) which comprises a first electrode (E1), a second electrode (E2) and an interposed, movable third electrode (E3) of display elements (DE) of the device (EFD, UG). The second electrode of each element is coupled to a corresponding picture voltage sampling output. The third electrode, which is interconnected with all elements, receives from a control voltage generator (UG) a control voltage (SE3) which varies over the television field period and includes a reset pulse for resetting the third to the second electrode and thereafter has a linearly decreasing control voltage. The first electrode, which is common to all elements, is thereby supplied during the field period with a constant control voltage (SE1).

Abstract: An "Integrated Injection Logic" integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via rectifying junctions, to predetermined zones of the circuit to be biased. Such zones are preferably biased by charge carriers which are collected by such zones from one of the layers of the current injector. The circuit also preferably includes a region for reducing carrier injection from a predetermined zone.

Abstract: A semiconductor device is fabricated by a process in which an aperture (4) is an insulating layer (3) along a surface (2) of a semiconductor body is utilized in defining the lateral extents of zones (6, 7, and 8) in a circuit element of the device. In particular, the insulating layer is first provided with the aperture along the surface. A semiconductor layer (5) is formed on the insulating layer, including the portion within the aperture. Using the edge of the insulating layer along the aperture as a masking edge, a pair of opposite-conductivity dopants are introduced selectively into the aperture and a third dopant is introduced through all of the aperture into the body. The third dopant may be introduced into the body before the semiconductor layer is formed.

Abstract: A memory cell for a static memory, in which the number of control lines is reduced to a maximum of three by the use of a diode in one collector circuit and the series connection of a diode and a resistor in the other collector circuit of an Eccles-Jordan flip-flop, which diodes have an exponential characteristic with an exponent smaller than that of conventional diodes.

Abstract: An integrated circuit includes a number of diode-coupled gate circuits, each having an inverter transistor. The logic signals are coupled between the gate circuits by conductive tracks which also form the coupling diodes. These diodes are mono-poly or poly diodes, and are formed integrally with the conductive tracks to achieve a flexible yet simple construction.

Abstract: A memory cell for integration into a static memory includes two transistors with cross-coupled base and collector regions. The collector regions are connected to p-n junction diode load elements having at least one region of polycrystalline silicon material. The collector regions of the transistors are connected to the regions of the diodes which are of the same conductivity type as the collector regions.

Abstract: An "Integrated Injection Logic" integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via rectifying junctions, to predetermined zones of the circuit to be biased. Such zones are preferably biased by charge carriers which are collected by such zones from one of the layers of the current injector. The circuit also preferably includes a region for reducing carrier injection from a predetermined zone.

Abstract: The invention relates to a semiconductor device in which a crossing connection is realized by using parts of a layer of refractory conductive material already present for masking as a part of a current conductor separated from a crossing conductor by an insulation layer. The mask of refractory material may also define the regions in which switching transistors are realized. The invention results in important advantages, in connection with density and crossing connections, in particular in I.sup.2 L-circuits.

Abstract: A method of manufacturing a semiconductor device, in particular a monolithic integrated circuit having very small complementary transistors. According to the invention two surface zones are provided beside each other without a masking tolerance of which one is formed by diffusion from a thin silicon layer. The distance between the surface zones is determined by the width of an oxide strip formed on the surface and on the edge of the silicon layer. The oxide strip is obtained by an underetching process and by using a silicon nitride mask deposited with shadow effect.

Abstract: A multi-stage I.sup.2 L circuit includes a first switching transistor in a higher stage coupled as a bistable trigger to a second transistor in a lower stage. Additional circuitry is supplied to increase the switching speed of the I.sup.2 L circuit by draining stored charge from the base of the second transistor. Regenerative feedback is employed to enhance the effect.

Abstract: A random access memory (RAM) in which each memory cell includes a JFET having two gate electrodes selectable by means of a single word line and a single bit line. The JFETs have a common electrode formed from the substrate of a semiconductor body common to each of the memory cells, which serves as one of the main electrodes of each of the JFETs.