Abstract: The invention relates to the transmission of MPEG encoded television signals from a Video-On-Demand server (1) to a receiver (2) via a network (3). Non-linear playback functions such as ‘pause’ and ‘resume’ require a very accurate control of the bit stream, taking account of typical network aspects such as network latency and remultiplexing. In order to allow the receiver to flawlessly resume signal reproduction after a pause, position labels (p; 5, 6; 7a, 7b, 8a, 8b) are inserted into the bit stream at positions where the server can resume transmission of the signal after an interruption. Upon a pause request, the decoder initially continues the reproduction until such a position label is detected. The subsequent bits delivered by the network are ignored, i.e. they are thrown away. Upon a request to resume reproduction, the receiver requests the server to retransmit the signal starting at the detected position.

Abstract: The invention relates to the transmission of MPEG encoded television signals from a Video-On-Demand server (1) to a receiver (2) via a network (3). Non-linear playback functions such as ‘pause’ and ‘resume’ require a very accurate control of the bit stream, taking account of typical network aspects such as network latency and remultiplexing. In order to allow the receiver to flawlessly resume signal reproduction after a pause, position labels (p; 5,6; 7a,7b,8a,8b) are inserted into the bit stream at positions where the server can resume transmission of the signal after an interruption. Upon a pause request, the decoder initially continues the reproduction until such a position label is detected. The subsequent bits delivered by the network are ignored, i.e. they are thrown away. Upon a request to resume reproduction, the receiver requests the server to retransmit the signal starting at the detected position.

Abstract: A multimedia application title is stored for execution on different platforms. Associated to the title is an occurrence table that lists the number of occurrences of each of at least a substantial fraction of all operations in the application, and also an execution profile table that lists the relative execution occurrence frequencies of each of at least a substantial fraction of all operations in the application. When loading the application title, its occurrence and execution profile tables are accessed. Through OP2INS and MOPS2MIPS conversion data for each operation, memory and processing requirements for executing the title are evaluated and an evaluation result signalled to a user.

Abstract: Disclosed are a method and arrangement for accessing interactive audiovisual programs stored on a remote server (1) by a multimedia station (2). The audiovisual program is stored in the same format as it is stored on a CDi disc, i.e. in the form of sectors. Although based on the same data compression technology, the CDi video coding standard does not comply with the MPEG coding specification. Moreover, MPEG does not cover the handling of specific CDi features. In order to allow conventional CDi decoders to access remotely stored CDi applications via interactive networks (3,4), the interactive audiovisual program is transmitted as a private MPEG2 data stream, using the concept of MPEG's transport stream. The multimedia station comprises a network interface (7) having a circuit (72) which assembles the transport packets and applies the signal sectorwise to a "stripped" CDi player (5,6).

Abstract: The invention relates to the reception of MPEG encoded television signals from a Video-On-Demand server (1) via a network (3). Non-linear playback functions such as `pause` and `resume` require a very accurate control of the bit stream, taking account of typical network aspects such as network latency. The receiver (2) comprises a latency buffer (24) for storing the signal delivered while the reproduction is stalled. The pause and resume commands from the user are not forwarded to the server until the latency buffer reaches a predetermined fullness. This allows the receiver to resume flawlessly signal reproduction after a pause.

Abstract: Apparatus and methods for improving timing recovery of a system clock by causing its frequency to be within a specified tolerance range during a timing recovery acquisition period for the system clock. The apparatus includes a voltage controlled oscillator for producing the system clock and a non-volatile memory containing an offset value. The non-volatile memory provides an offset value (representing an offset voltage value) which assures that the voltage controlled oscillator receives a voltage value which causes the frequency of the system clock to be within a specified tolerance range. The apparatus may also include a write control unit for determining and updating the offset value for a next timing recovery acquisition period. The methods include steps for performing these operations.

Abstract: A delay circuit includes a first and a second switching transistor, each of which has a control electrode and a first and a second main electrode, a first and a second input of the delay circuit being coupled to the control electrode of the first switching transistor and the second switching transistor, respectively. A first and a second output of the delay circuit are coupled to the second electrode of the first and the second switching transistors, respectively. The first electrodes of the first and the second switching transistors are coupled to one another and, via a current source, to a first power supply terminal. The outputs are coupled to a second power supply terminal via respective load circuits. Respective clamp circuits are coupled to the outputs in order to limit maximum attainable differences between a voltage on the second power supply terminal on the one side and a voltage on the respective outputs on the other side.

Abstract: An integrated circuit comprises a time-discrete oscillator which generates numerical and time-discrete phase values of an oscillator signal. The circuit also comprises a time-continuous oscillator which generates a time-continuous oscillation signal. The circuit comprises a phasemeter which is coupled to the time-continuous oscillator in order to sample phase values of the time-continuous signal. The difference between the generated phase values and the sampled phase values is measured in a comparator circuit. This difference is utilized in a phase-locked loop in order to readjust the frequency of the time-continuous oscillator, so that the time-continuous oscillation is latched to the time-discrete oscillation. The phase comparison can thus be executed in a substantially time-discrete manner. As a result, the operational reproducibility of the circuit is very high.

Abstract: A coupling network for a data processor is described, including, one or more cross bar switches having inputs and outputs and one or more arrays of silos. A series connection is formed in which these components are alternately arranged in a succession having at least three elements. A retrocoupling network is used for coupling outputs of a data processor to its inputs, and it also provides external communication. The configuration offers ample freedom of mapping, notably in cyclostatic processors.

Abstract: The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

Abstract: A data processing system buffers sequential data for the duration of cyclically recurrent delay times. Memory location allocation is performed in such a way, that the memory is used efficiently without data-shifting after a read-out, and that the address generator is fairly simple.

Abstract: The invention describes a processor system suitable for processing video signal samples on a real-time basis. Signals are derived from the samples for driving an imaging unit. For this purpose, one or more processor modules are provided with processor elements, operating in parallel in time, which are connected to a crossbar switch. A module contains at least one arithmetic/logic processor element and at least one memory processor element. Moreover, there is a clock device, the frequency of which bears a fixed relationship to the frequency with which the video signal samples are obtained.

Abstract: A data processor system having at least one arithmetic/logic processor element and at least one memory processor element which can be coupled in circuit using a crossbar switch. The arithmetic/logic processor element is provided with an ALU and a program memory. The ALU has an input for instructions. The instructions can be made up of data from the program memory and data from the crossbar switch via a channel specifically present for the purpose.

Abstract: In an adaptive electronic buffer system in which a set circuit generates logic set signals for the buffer circuits, parallel sub-buffers are switched on or off by the set signals, so that the specified charging and discharging times of the output can be achieved. This setting compensates for the manufacturing process variations and operating conditions (temperature, supply voltage) of the buffer circuits. The spread in the output conductance is reduced, thus reducing the risk of fast current variations, inductive voltage peaks and the associated loss of data.

Abstract: In order to reduce the likelihood of incorrect states being transferred from one cross-coupled transistor pair to the next in a frequency divider which comprises at least two such pairs (6a, 7a and 8a, 9a) which are energized alternately by means of a switchable current source arrangement (5) and which are inter-coupled to form a cyclic arrangement by means of data transfer transistors (6b, 7b, 8b and 9b) energized from the same outputs (22, 23) of the current source arrangement, the transistors employed are of the insulated gate field effect type. The channel width-to-length ratios of the pair transistors (6a, 7a, 8a, 9a) may be chosen to be different from the corresponding ratios for the data transfer transistors (6b, 7b, 8b, 9b) in order to improve either the high-frequency or the low frequency performance in accordance with the sign of such difference.