Abstract: A high speed I.sup.2 L circuit having a topology which is based on a layout of parallel arranged gate circuits in which the inverter transistors of each gate circuit are arranged in a row and below the signal lines to which they are connected, said signal lies extending transversely to the rows, while the complementary transistors for the current supply of the inputs of the gate circuits are situated laterally beside the signal lines. Said layout facilitates the designing of comparatively compact I.sup.2 L circuits in which various measures to increase their speed can be taken, for example, the use of dielectric isolation, reduction of the input series resistance, reversal of the doping profile and the application of a potential difference between the bases of the complementary transistors and the common emitter of the inverter transistors.

Abstract: An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.

Abstract: A logic circuit in I.sup.2 L wherein across the base-emitter paths of the NPN-transistors diodes are connected in order to reduce the propagation delay time of the logic circuit.

Abstract: A method of making a semiconductor device is described in which opposite-type impurities are introduced into the same surface of a substrate in such manner that the region of impurities of the opposite-type to that of the substrate overlaps completely the other substrate surface region. Then an epitaxial layer is grown on the surface of the substrate. There is thus formed two buried layers of which the one with the same type conductivity of the substrate is completely separated and isolated from the latter by the buried layer of opposite-type conductivity. Methods are also described for the manufacture of complementary bipolar transistors, in which the pnp type is made by the above described method.