Abstract: A power converter uses a charge pump divider that includes a capacitive divider core and a phase clock generator. The capacitive divider core has an input for receiving an input voltage and an output for providing an output voltage. In a first phase the capacitive divider core is adapted to couple a flying capacitor in series with an output capacitor. In a second phase the capacitive divider core is adapted to couple the flying capacitor in parallel with the output capacitor. The phase clock generator activates a first phase clock indicating the first phase when a flying voltage across the flying capacitor is less than a predetermined portion of the input voltage minus a peak voltage, and subsequently activates a second phase clock indicating the second phase when the flying voltage exceeds the predetermined portion of the input voltage plus the peak voltage.

Abstract: An integrated circuit having a plurality of integrated circuit portions where each of the plurality of integrated circuit portions receives a corresponding voltage of a plurality of voltages. Selection circuitry selects a selected voltage of the plurality of voltages and provides an indication of the selected voltage to adjust the supply voltage to the integrated circuit. In one embodiment, the indication may correspond to an analog signal proportional to the selected voltage such as e.g. at the selected voltage or at a voltage less than or greater than the selected voltage. In one embodiment, the selected voltage corresponds to a maximum voltage of the plurality of voltages which may be selected based on sensing the plurality of voltages or based on a plurality of voltage level indicators which set the plurality of voltages. A power supply system, coupled to the integrated circuit, may be used to receive the indication of the selected voltage and adjust the supply voltage based on the indication.