Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract: A method of forming a gate metallization in a semiconductor integrated circuit by forming a polycrystalline silicon layer over a gate dielectric layer and then converting the polycrystalline silicon layer into tungsten or tungsten silicide by exposing the polycrystalline silicon to tungsten hexafluoride gas. The method enables the formation of polycrystalline silicon and tungsten or tungsten silicide in the same process cycle in the same reactor or in two similarly configured reactors or in two similarly configured clustered reactors.

Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract: A method to prepare thermal reactors for operation after installation, modification, upgrade and routine preventive maintenance operations. Variations in reaction rate across a wafer surface are used to determine corresponding variations in surface temperature across the wafer surface. Surface temperature variations results in thickness variations of a chemically deposited layer. For selected thicknesses, a chemically deposited layer is transparent and exhibits color variations corresponding to the thickness variations that result from the surface temperature variations. These color variations are then correlated to surface temperature variations to enable wafer heating adjustments to reduce surface temperature variations.