Abstract: An organic field-effect transistor is disclosed in which an insulating layer having a thickness of 0.3 m or less is provided on a substantially planar electrode layer. This transistor has a channel length down to 2 m, satisfying the condition for voltage amplification well below 10V, and has an on/off ratio of about 25.

Abstract: A practical method of manufacturing an organic field-effect transistor is disclosed. By applying the insulating layer having a thickness of 0.3 &mgr;m or less to a substantially planar electrode layer, an organic field-effect transistor can be made having a channel length down to 2 &mgr;m, satisfying the condition for voltage amplification at voltages well below 10 V, and having an on/off ratio of about 25.

Abstract: A practical method of manufacturing an organic field-effect transistor is disclosed. By applying the insulating layer, preferably having a thickness of 0.3 &mgr;m or less to a substantially planar electrode layer, an organic field-effect transistor can be made having a channel length down to 2 &mgr;m, satisfying the condition for voltage amplification at voltages well below 10 V, and having an on/off ratio of about 25.

Abstract: A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip is used to make a notch in a vertical interconnect area of two organic electrically conducting areas separated from each other by an organic electrically insulating area. The method is used in the manufacture of integrated circuits consisting substantially of organic materials.

Abstract: A laminated structure (1) comprising a substrate (3) and a polymer layer (5) is provided. The polymer layer consists of conductive areas (7) having a sheet resistance of maximally 1000 .OMEGA./square. The adjacent parts of the polymer layer are substantially non-conductive and have a sheet resistance which is a factor of 10.sup.6 higher. An electrodeposited metal layer (9), for example of copper, is present on the conductive areas (7).A simple method of photochemically generating the conductive pattern (7) which can be reinforced in an aqueous metal-salt solution by electrodeposition of a metal layer (9) is also provided and most preferably the conductive pattern is inter alia, the patterned exposure of a layer of 3,4-ethylene dioxythiophene or polyaniline. The method can very suitably be used for the manufacture of metal patterns on insulating substrates, such as printed circuit boards.

Abstract: A solution of monomers, oligomers or polymers and a suitable oxidation agent can be stable if the solution also comprises a base. By spin coating this solution onto a substrate, a layer can be formed which, after patterned irradiation, yields a pattern of a doped conductive polymer which is formed in situ, the exposed and unexposed areas exhibiting a large difference in conductivity. A description is given of, inter alia, the patterned irradiation of a layer of 3,4-ethylenedioxythiophene. If desired, the conductive polymer pattern can subsequently be metallized in an electroplating bath. The method provides, inter alia, a simple process of manufacturing metal patterns on insulating substrates, such as printed circuit boards.

Abstract: A laminated structure (1) comprising a substrate (3) and a polymer layer (5) is provided. The polymer layer consists of conductive areas (7) having a sheet resistance of maximally 1000 .OMEGA./sqaure. The adjacent parts of the polymer layer are substantially non-conductive and have a sheet resistance which is a factor of 10.sup.6 higher. An electrodeposited metal layer (9), for example of copper, is present on the conductive areas (7).A simple method of photochemically generating the conductive pattern (7) which can be reinforced in an aqueous metal-salt solution by electrodeposition of a metal layer (9) is also provided and most preferably the conductive pattern is inter alia, the patterned exposure of a layer of 3,4-ethylene dioxythiophene or polyaniline. The method can very suitably be used for the manufacture of metal patterns on insulating substrates, such as printed circuit boards.