Abstract: A processor-implemented method includes generating, by a scheduling model, a group of schedules from a computation graph associated with a task, each node on the computation graph being associated with an operation of an artificial neural network, each schedule of the group of schedules associating each node of the computation graph with a processor of a group of processors of a hardware device. The processor-implemented method also includes testing one or more schedules of the group of schedules on the hardware device or a model of the hardware device. The processor-implemented method further includes selecting a schedule of the one or more schedules based on testing the one or more schedules, the selected schedule satisfying a selection condition.

Abstract: A processor-implemented method for generating a schedule for executing operations of a compute graph includes receiving a graph including multiples nodes connected by edges. Each of the multiple nodes represents an operation to be executed. A set of sequences for executing the nodes is determined based on one or more precedence constraints. One or more sequences are selected from the set of sequences based on a memory constraint associated with a device for executing the nodes. A schedule for executing the nodes on the device is generated based on the selected one or more sequences.

Abstract: A processor-implemented method for generating a topological order using an artificial neural network (ANN) includes receiving a set of tasks to be performed. The tasks are represented in a graph including multiple nodes connected by edges. Each node corresponds to a task in the set of tasks. A scheduling priority is assigned to each node in the graph. A next node of potential next nodes is selected according to a probability of each of the potential next nodes based on the assigned scheduling priorities and a topology of the graph. A topological order of the tasks is generated by repeating the selection of the next node.