Abstract: A ball grid array device includes a monitoring circuit of inactive solder joints and a processor such as a field programmable gate array (FPGA) or other processor capable of determining the open or closed status of the monitoring circuit. The monitoring circuit traverses one or more of the solder joints between components being joined, such as a printed circuit board and an integrated circuit device. In certain embodiments, the inactive solder joints may be located within regions of the ball grid array that are predisposed to failure, such as at the periphery or corners of the printed circuit board, or proximate to regions that experience a broad range of operating temperatures. The failure of a solder joint within the monitoring circuit can be used to schedule maintenance of the ball grid array device prior to failure of an active solder joint.

Abstract: An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.

Abstract: An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.