Abstract: A method for operating a resistivity changing memory including applying a programming voltage to a resistivity changing memory cell to define a programmed state and applying a refresh voltage to the resistivity changing memory cell for maintaining the programmed state of the resistivity changing memory cell. In one embodiment, the refresh voltage is less than the programming voltage.

Abstract: A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode, discharging the read capacity over the active material of the memory cell, and determining the memory state of the memory cell in dependence on a change of the voltage during the discharge of the read capacity.

Abstract: An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

Abstract: The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.

Abstract: According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the first potential, thereby generating a memory state sensing current flowing through the resistivity changing memory cell; controlling the strength of the second potential in dependence on the strength of the memory state sensing current such that the strength of the memory state sensing current is kept constant.

Abstract: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Abstract: The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.

Abstract: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Abstract: A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of resistivity changing memory cells, the at least one resistivity changing reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal.

Abstract: According to one embodiment of the present invention, a memory device includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, and a plurality of select devices. Each current path output terminal is connected to at least one different current path output terminal via at least one select device.

Abstract: A memory device and method for operating a memory device is described. In one embodiment, the memory device has at least one memory cell including an active material, a current supply line, and a first switching device for switching a first current from the current supply line through the active material. The memory cell additionally includes at least one further switching device for switching a further current from the current supply line through the active material.

Abstract: A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.

Abstract: The invention relates to a method for reading a memory datum from a resistive memory cell comprising a selection transistor which is addressable via a control value, the method comprising detecting a cell current flowing through the resistive memory cell, setting the control value depending on the detected cell current, and providing an information associated to the control value as a memory datum.

Abstract: An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line of the plurality of bit lines to select a row of storage devices, and the second voltage is applied to each of further lines except for a further line being connected to the storage devices of the selected column.

Abstract: To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

Abstract: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

Abstract: A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

Abstract: A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

Abstract: A memory device, and method of operating the same, wherein the device includes resistive memory cells being switched between a low-resistive state and a high-resistive state; an evaluation unit, being coupled to a resistive memory cell to determine a resistive state of the resistive memory cell; and a voltage regulation circuit, being coupled to the resistive memory cell and to the evaluation unit. The voltage being applied to the resistive memory cell is regulated with respect to a target voltage.

Abstract: A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode, discharging the read capacity over the active material of the memory cell, and determining the memory state of the memory cell in dependence on a change of the voltage during the discharge of the read capacity.