Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

Abstract: A system is provided. In some examples, the system includes a first peripheral circuit and a memory management circuit coupled to the first peripheral circuit. The memory management circuit comprises a first table that associates virtual identification values with address space select values. The system also includes a transaction mapper circuit coupled to the memory management circuit. The transaction mapper circuit comprises a second table that associates virtual identification values with bus-device-function values.

Abstract: A system is provided. In some examples, the system includes a first peripheral circuit and a memory management circuit coupled to the first peripheral circuit. The memory management circuit comprises a first table that associates virtual identification values with address space select values. The system also includes a transaction mapper circuit coupled to the memory management circuit. The transaction mapper circuit comprises a second table that associates virtual identification values with bus-device-function values.

Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.