Abstract: In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.

Abstract: Amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include multiple driver circuits and a control circuit. The control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits, according to an input signal to be reproduced by one or more of the multiple amplifier driver circuits. The control circuit determines a splice point at which the control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits.

Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises: primary driver circuitry coupled to a primary signal path and operable to drive the load with a playback signal in a first mode of operation of the circuitry, wherein a playback signal comprises a signal that drives the load to generate a desired output; auxiliary driver circuitry coupled to an auxiliary signal path; an auxiliary current sense resistor in the auxiliary signal path; and current detection circuitry coupled to the auxiliary current sense resistor and configured to generate a signal indicative of a current through the load. One of the primary driver circuitry and the auxiliary driver circuitry is operable to drive the load with a pilot signal in a second mode of operation of the circuitry, wherein a pilot signal comprises a signal having a predefined frequency or frequency content and a predefined magnitude.

Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage.

Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises: primary driver circuitry coupled to a primary signal path and operable to drive the load with a playback signal in a first mode of operation of the circuitry, wherein a playback signal comprises a signal that drives the load to generate a desired output; auxiliary driver circuitry coupled to an auxiliary signal path; an auxiliary current sense resistor in the auxiliary signal path; and current detection circuitry coupled to the auxiliary current sense resistor and configured to generate a signal indicative of a current through the load. One of the primary driver circuitry and the auxiliary driver circuitry is operable to drive the load with a pilot signal in a second mode of operation of the circuitry, wherein a pilot signal comprises a signal having a predefined frequency or frequency content and a predefined magnitude.

Abstract: Amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include multiple driver circuits and a control circuit. The control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits, according to an input signal to be reproduced by one or more of the multiple amplifier driver circuits. The control circuit determines a splice point at which the control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits.

Abstract: A Data Storage Device (DSD) includes a memory for storing data, and a controller configured to execute firmware or code to perform a task. While performing the task, the controller is further configured to assign unique identifiers to respective firmware or code portions that are executed to perform the task, and create a list or data structure including the unique identifier assigned to the firmware or code portion that created the task. A unique identifier is added to the list or data structure for each firmware or code portion executed for the task. The list or data structure indicates the order in which the firmware or code portions are executed.

Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor.

Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.

Abstract: In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.

Abstract: Circuitry for driving a load, the circuitry comprising: driver circuitry; and load sensing circuitry, wherein the circuitry is operable in: a driving mode of operation in which the driver circuitry supplies a drive signal to a load coupled to the circuitry; and a load sensing mode of operation, for estimating a characteristic of a load coupled to the circuitry based on a signal output by the load sensing circuitry in response to a stimulus signal, wherein the circuitry is configured to, in response to a request for operation of the circuitry in the load sensing mode: compare an indication of a current through the load to a predefined threshold; and if the indication of the current through the load meets the predefined threshold, prevent or delay operation in the load sensing mode.

Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.

Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.

Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage.

Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises: primary driver circuitry coupled to a primary signal path and operable to drive the load with a playback signal in a first mode of operation of the circuitry, wherein a playback signal comprises a signal that drives the load to generate a desired output; auxiliary driver circuitry coupled to an auxiliary signal path; an auxiliary current sense resistor in the auxiliary signal path; and current detection circuitry coupled to the auxiliary current sense resistor and configured to generate a signal indicative of a current through the load. One of the primary driver circuitry and the auxiliary driver circuitry is operable to drive the load with a pilot signal in a second mode of operation of the circuitry, wherein a pilot signal comprises a signal having a predefined frequency or frequency content and a predefined magnitude.

Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage.

Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.

Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor.

Abstract: Class-D amplifiers and modulators therefor provide control of the DC operating point of the outputs of the amplifiers. The modulators generate a sum and difference signal using combiners and introduce the sum signal to a reference input of the quantizer, while the quantization input of the quantizer receives the difference signal. A difference mode loop filter circuit may filter the difference signal and a common mode loop filter may filter the sum signal. Outputs of the quantizer operate a pair of switching circuits to provide either a differential output with the sum signal set to a constant voltage and the difference signal provided by the signal to be reproduced, or a pair of single-ended outputs with the individual input signals used to generate the sum and difference signal, and selection of a differential or dual single-ended operating mode may be performed by a control circuit that reconfigures the combiners.

Abstract: A system may include an output driving stage comprising a first switch configured to selectively open and close an electrical path between a first supply voltage and an output terminal of the output driving stage and a second switch configured to selectively open and close an electrical path between a second supply voltage and the output terminal of the output driving stage, wherein the second supply voltage is lower than the first supply voltage. The system may also include detection and protection circuitry configured to monitor a physical quantity indicative of the second supply voltage and responsive to the physical quantity exceeding an overvoltage threshold, electrically isolate the output terminal from the second supply voltage.