Abstract: Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. The entry includes an indicator indicating that the information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host.

Abstract: Techniques are disclosed, including a method that can include entering a first mode of operation of an apparatus including a memory device, receiving first information indicative of a subsequent download of second information at the memory device, the memory device including a first group of cells configured as multi-level cell (MLC) memory, in response to receipt of the first information, converting a portion of the first group of cells from configuration as MLC memory to configuration as single-level cell (SLC) memory, receiving and storing the second information at the memory device, and upon exiting the first mode of operation, reconfiguring at least a portion of the SLC memory to MLC memory while simultaneously maintaining storage of the second information within the memory device.

Abstract: Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. The entry includes an indicator indicating that the information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host.

Abstract: Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. The entry includes an indicator indicating that the information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host.

Abstract: Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. The entry includes an indicator indicating that the information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host.

Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.