Abstract: A detector for measuring a resistance of a variable resistance sensor (VRS) that varies with respect to a time-varying stimulus (e.g., temperature) includes a voltage reference having variation with respect to operating conditions and a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector. The sensed voltage includes error due to the variation of the voltage reference. The detector also includes a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an ADC that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance. The PGA is non-varying with respect to the time-varying stimulus.

Abstract: A detector for measuring a resistance of a variable resistance sensor (VRS) that varies with respect to a time-varying stimulus (e.g., temperature) includes a voltage reference having variation with respect to operating conditions and a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector. The sensed voltage includes error due to the variation of the voltage reference. The detector also includes a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an ADC that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance. The PGA is non-varying with respect to the time-varying stimulus.

Abstract: A system includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g., temperature) and is proportional to the unknown scalar.

Abstract: A portable audio device may be configured to measure load characteristics of headphones. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load. These characteristics may be measured by an audio component, such as an audio codec chip or integrated circuit (IC) controller, and reported to software or firmware executing on a processor coupled to the audio component. The software or firmware may then take action based on the measured load characteristics. For example, the load characteristics may be compared to a database of headphones and their known load characteristics to determine a particular headphone model or type of headphone attached to the audio output. The processor may then apply an appropriate equalization curve.

Abstract: A digital volume control may be implemented in a digital-to-analog controller (DAC) when an output rate of the DAC is higher than the input rate. The upsampling conversion process from the digital input to analog output may be controlled to adjust a volume of an output signal produced from the digital signals. The frames produced by the upsampling conversion process may include a fraction of scheduling blocks filled with the input data bit, where the fraction is based on a desired volume. The generated frames are provided to a finite impulse response (FIR) filter that produces an analog signal with a magnitude proportional to the determined fraction of scheduling blocks.

Abstract: A digital volume control may be implemented in a digital-to-analog controller (DAC) when an output rate of the DAC is higher than the input rate. The upsampling conversion process from the digital input to analog output may be controlled to adjust a volume of an output signal produced from the digital signals. The frames produced by the upsampling conversion process may include a fraction of scheduling blocks filled with the input data bit, where the fraction is based on a desired volume. The generated frames are provided to a finite impulse response (FIR) filter that produces an analog signal with a magnitude proportional to the determined fraction of scheduling blocks.

Abstract: A portable audio device may be configured to measure load characteristics of headphones. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load. These characteristics may be measured by an audio component, such as an audio codec chip or integrated circuit (IC) controller, and reported to software or firmware executing on a processor coupled to the audio component. The software or firmware may then take action based on the measured load characteristics. For example, the load characteristics may be compared to a database of headphones and their known load characteristics to determine a particular headphone model or type of headphone attached to the audio output. The processor may then apply an appropriate equalization curve.

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.