Patents by Inventor Cory Lappi

Cory Lappi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12699516
    Abstract: Methods and related systems are provided. A method is performed by a memory device including memory, where the memory device is coupled to a host device. A method includes receiving, at the memory device, a command from the host device to read a portion of the memory, determining, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads, and providing, by the memory device, based on the command, the host device with data stored in the portion of memory using a plurality of throttled read operations. Each throttled read operation of the plurality of throttled read operations includes no more than the threshold number of reads and is performed based on the delay.
    Type: Grant
    Filed: December 18, 2024
    Date of Patent: August 4, 2026
    Assignee: Solidigm Inc.
    Inventors: Ning Wu, Mohammad Nasim Imtiaz Khan, Cory Lappi, Jozsef Dudas
  • Publication number: 20260169636
    Abstract: Methods and related systems are provided. A method is performed by a memory device including memory, where the memory device is coupled to a host device. A method includes receiving, at the memory device, a command from the host device to read a portion of the memory, determining, by the memory device, for the portion of the memory, a threshold number of reads and a delay associated with the threshold number of reads, and providing, by the memory device, based on the command, the host device with data stored in the portion of memory using a plurality of throttled read operations. Each throttled read operation of the plurality of throttled read operations includes no more than the threshold number of reads and is performed based on the delay.
    Type: Application
    Filed: December 18, 2024
    Publication date: June 18, 2026
    Inventors: Ning Wu, Mohammad Nasim Imtiaz Khan, Cory Lappi, Jozsef Dudas
  • Patent number: 12638980
    Abstract: Mechanisms for providing solid-state drives (SSDs) (such as NAND SSDs) with a dynamic system area are provided. In some embodiments, the mechanism includes: determining a memory die from a plurality of individual memory dies on which system-related data is stored in a reserved band from a plurality of bands; determining lifetime information associated with the memory die on which the system-related data is stored in the reserved band; in response to determining that the lifetime information associated with the memory die is greater than a threshold value, determining unused dies from the plurality of individual memory dies on which the reserved band does not contain the system-related data; selecting at least one unused die based on the determined unused dies; and storing the system-related data in the reserved band of the selected unused die.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: May 26, 2026
    Assignee: SK hynix NAND Product Solutions Corporation
    Inventors: Cory Lappi, Ning Wu, Jozsef Dudas
  • Patent number: 12524336
    Abstract: This invention is directed to managing data storage in a memory system. The memory system receives a host request for an erase operation on a first erasable unit of a first memory block. In response to the host request, the memory system identifies an unused erasable unit of a second memory block in the memory system, remaps the first erasable unit of the first memory block to the unused erasable unit of the second memory block, and applies the erase operation on the unused erasable unit of the second memory block in place of the first erasable unit of the first memory block. In some embodiments, at a time of receiving the host request, the memory system further includes a space reserve of over-provisioning, and the second memory block is different from the space reserve. In some embodiments, the second memory block is moved offline to join the space reserve.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: January 13, 2026
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Chaohong Hu, Ning Wu, Cory Lappi
  • Publication number: 20250199691
    Abstract: Mechanisms for providing solid-state drives (SSDs) (such as NAND SSDs) with a dynamic system area are provided. In some embodiments, the mechanism includes: determining a memory die from a plurality of individual memory dies on which system-related data is stored in a reserved band from a plurality of bands; determining lifetime information associated with the memory die on which the system-related data is stored in the reserved band; in response to determining that the lifetime information associated with the memory die is greater than a threshold value, determining unused dies from the plurality of individual memory dies on which the reserved band does not contain the system-related data; selecting at least one unused die based on the determined unused dies; and storing the system-related data in the reserved band of the selected unused die.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Inventors: Cory Lappi, Ning Wu, Jozsef Dudas
  • Publication number: 20250110866
    Abstract: This invention is directed to managing data storage in a memory system. The memory system receives a host request for an erase operation on a first erasable unit of a first memory block. In response to the host request, the memory system identifies an unused erasable unit of a second memory block in the memory system, remaps the first erasable unit of the first memory block to the unused erasable unit of the second memory block, and applies the erase operation on the unused erasable unit of the second memory block in place of the first erasable unit of the first memory block. In some embodiments, at a time of receiving the host request, the memory system further includes a space reserve of over-provisioning, and the second memory block is different from the space reserve. In some embodiments, the second memory block is moved offline to join the space reserve.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Chaohong HU, Ning WU, Cory LAPPI
  • Patent number: 11615805
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: March 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Cory Lappi, William Jared Walker
  • Patent number: 11416417
    Abstract: A method is provided that includes reading data in a storage medium, detecting, during the reading of the data in the storage medium, by a controller a change in an encryption/decryption scheme used to read and write the data in the storage medium, in response to detecting the change in encryption/decryption scheme in the data, causing, by the controller, a logical block address to return an indication of being written in zeros when a physical block address associated with the logical block address encrypted using an first encryption/decryption scheme, and causing, by the controller, a write channel to write zeroes using a second encryption/decryption scheme to the physical block address.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker
  • Patent number: 11288204
    Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 29, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Cory Lappi, Nicholas Edward Ortmeier, William Jared Walker
  • Publication number: 20220076696
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Cory LAPPI, William Jared WALKER
  • Patent number: 11226811
    Abstract: The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 18, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 11195548
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 7, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Cory Lappi, William Jared Walker
  • Publication number: 20210232385
    Abstract: The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cory LAPPI, William Jared WALKER, Xin CHEN
  • Patent number: 10990380
    Abstract: The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 27, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 10922070
    Abstract: A method for performing a download operation is described comprising detecting an updated firmware for installation, transmitting at least one slice of the updated firmware from an updated firmware location to a second firmware location, determining if a synchronization has completed with the at least one slice of the updated firmware and determining if additional slices are to be synchronized when the synchronization has completed with the at least one slice of the updated firmware.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Patent number: 10922242
    Abstract: The present disclosure describes logical to physical tables that are configured to provide multiple sector support and provide for help in processing of data when a sector is mapped or unmapped. In the cases where sectors are unmapped, the present disclosure provides mechanisms to concurrently support multiple unique unmapped data patterns depending upon the specific type of unmapped sector.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, William Jared Walker, Darin Edward Gerhart
  • Patent number: 10831657
    Abstract: The present disclosure generally relates to a storage device sensing critical failure or PLI events and writing the debug data to a memory device so that when boot-up occurs, at least some debug data is available. A dedicated hardware unit detects when one or more critical failure conditions occur by monitoring the one or more critical failure conditions. The critical failure conditions being detected or sensed triggers the dedicated hardware unit to automatically write debug data stored in a volatile memory device to a non-volatile memory device. The debug data stored in the non-volatile memory device provides a critical failure or PLI trace to determine what occurred leading up to and during a critical failure event. By writing the debug data to the non-volatile memory device, the critical failure trace may be accessed and analyzed after the device powers down or fails.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 10, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventors: Cory Lappi, William Jared Walker, Xin Chen
  • Publication number: 20200349086
    Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Darin Edward GERHART, Cory LAPPI, Nicholas Edward ORTMEIER, William Jared WALKER
  • Publication number: 20200342898
    Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Cory LAPPI, William Jared WALKER
  • Publication number: 20200310989
    Abstract: A method is provided that includes reading data in a storage medium, detecting, during the reading of the data in the storage medium, by a controller a change in an encryption/decryption scheme used to read and write the data in the storage medium, in response to detecting the change in encryption/decryption scheme in the data, causing, by the controller, a logical block address to return an indication of being written in zeros when a physical block address associated with the logical block address encrypted using an first encryption/decryption scheme, and causing, by the controller, a write channel to write zeroes using a second encryption/decryption scheme to the physical block address.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 1, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Cory Lappi, Daniel Robert Lipps, William Jared Walker