Patents by Inventor Cosmin Iorga
Cosmin Iorga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949587Abstract: A method includes receiving, at an unmanaged switch, a link-aggregation control protocol (“LACP”) protocol data unit (“PDU”) on each port of two or more connections to be in a link-aggregation group (“LAG”). The ports are in the unmanaged switch, which is unconfigured for LACP and is connected over the connections to a managed switch configured for LACP. The method includes, in response to the ports that received an LACP PDU being unconfigured for LACP, configuring each port receiving an LACP PDU for LACP, creating a LAG that includes the connections of the ports that received the LACP PDUs, and starting an LACP timer. The method includes, in response to determining that the LACP timer has expired, clearing the LACP configuration of the ports configured for LACP. The LACP timer expires in response to the ports in the LAG not receiving additional LACP PDUs prior to expiration of a timer period.Type: GrantFiled: September 30, 2021Date of Patent: April 2, 2024Assignee: Lenovo Global Technology (United States) Inc.Inventors: Corneliu-ilie Calciu, Radu Mihai Iorga, George-Andrei Stanescu, Bogdan-Cosmin Chifor
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Publication number: 20240080016Abstract: A pulse filter circuit is configured to eliminate pulses that are less than a specified duration and pass those that are greater than the specified duration. A buffer receives a signal and applies the buffered signal to a resistance-capacitance charging-discharging circuit (e.g., RC filter). When the output of the RC filter has, in response to the buffered signal, charged or discharged, as appropriate, to cause the output of a slicer to change, logic circuitry controls switching circuitry to pull the output of the RC filter to be fully charged or discharged, respectively. In this manner, pulses that are too short to charge/discharge the RC filter enough to cross the threshold of the slicer do not reach the slicer circuit output, but pulses that are long enough to cross the slicer threshold are transmitted by the slicer.Type: ApplicationFiled: August 22, 2023Publication date: March 7, 2024Inventors: Cosmin IORGA, Ruibing ZHANG
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Patent number: 11921841Abstract: Secure updating of strong passwords in a composable system, includes: during deployment of the composable system, requesting, by a central controller in the composable system, device information from a device vendor, the device information specifying a number of expected devices for the composable system; checking, by the central controller, a number of discovered devices against the number of expected devices; only upon discovering all the expected devices, updating, by the central controller, a password for all the devices in the composable system; and upon discovering fewer than the total number of expected devices, halting, by the central controller, deployment of the composable system.Type: GrantFiled: September 30, 2021Date of Patent: March 5, 2024Assignee: LENOVO GLOBAL TECHNOLOGY (UNITED STATES) INC.Inventors: Radu Mihai Iorga, Bogdan-Cosmin Chifor, Anda-Maria Nicolae, Crina-Elena Untea, Corneliu-Ilie Calciu
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Patent number: 11782476Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.Type: GrantFiled: November 18, 2021Date of Patent: October 10, 2023Assignee: Rambus Inc.Inventors: Panduka Wijetunga, Marcial Chua, Srinivas Satish Babu Bamdhamravuri, Abhishek Desai, Philip Lu, Cosmin Iorga
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Publication number: 20230080033Abstract: Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.Type: ApplicationFiled: August 30, 2022Publication date: March 16, 2023Inventor: Cosmin Iorga
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Publication number: 20220179444Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.Type: ApplicationFiled: November 18, 2021Publication date: June 9, 2022Inventors: Panduka Wijetunga, Marcial Chua, Srinivas Satish Babu Bamdhamravuri, Abhishek Desai, Philip Lu, Cosmin Iorga
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Patent number: 10560075Abstract: Measurement of power distribution network (PDN) Z-parameters and S-parameters of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks and I/O blocks commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. The measured models include the PDN elements on the PLD die, PLD package, and PCB. The S-parameter and Z-parameter models can be then used in circuit simulation tools to evaluate the power supply noise in the PLD logic core and the timing jitter in the PLD I/O data links.Type: GrantFiled: June 15, 2018Date of Patent: February 11, 2020Inventor: Cosmin Iorga
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Patent number: 9673972Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.Type: GrantFiled: October 3, 2016Date of Patent: June 6, 2017Assignee: INPHI CORPORATIONInventors: James L. Gorecki, Jiayun Zhang, Marcial K. Chua, Cosmin Iorga
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Patent number: 9571077Abstract: A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out falling edge according to an old phase interpolator code input, disabling a falling edge ramp signal while updating a falling edge interpolator, enabling the rising edge ramp signal and generating a new clock out rising edge according to a new phase interpolator code input, and enabling the falling edge ramp signal and generating a new clock out falling edge according to the new phase interpolator code input.Type: GrantFiled: July 13, 2015Date of Patent: February 14, 2017Assignee: RAMBUS INC.Inventors: Cosmin Iorga, James L. Gorecki
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Patent number: 9564909Abstract: A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.Type: GrantFiled: September 22, 2015Date of Patent: February 7, 2017Assignee: Rambus Inc.Inventors: Cosmin Iorga, Sriram Narayan
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Publication number: 20170026167Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.Type: ApplicationFiled: October 3, 2016Publication date: January 26, 2017Inventors: James L. GORECKI, Jiayun ZHANG, Marcial K. CHUA, Cosmin IORGA
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Patent number: 9548726Abstract: A driver integrated circuit (IC) device. The driver device can include a front-end module, a pre-driver module, and a driver module coupled to a transmission line path. The pre-driver module can be coupled to the front-end module and can include one or more delay adjust capacitor modules, and one or more pull-down control modules. The driver module can be coupled to the pre-driver module, the driver module including one or more pull-down control logic modules. This driver device can configured in several implementations to provide control and programmability of a driver slew rate to maximize a signal integrity eye opening.Type: GrantFiled: February 13, 2015Date of Patent: January 17, 2017Assignee: INPHI CORPORATIONInventors: Cosmin Iorga, Jeffrey C. Yen
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Patent number: 9537475Abstract: A method and device for dynamically updating a phase interpolator circuit module using an update control circuit module. The method can include providing the phase interpolator with a set of input clock phases to produce a clock signal. The update control module can generate a blanking signal in response to an update signal and apply an update process that stops an old clock output signal after a last clock pulse. The update control module can then update phase select multiplexers for a rising edge integrator and falling edge integrator according to a new phase interpolator code. The update control module can determine a phase jump code and then release the blanking signal during a discharge time interval of the rising edge integrator following a phase jump duration according to the phase jump code. Afterwards, the phase interpolator module can generate the new clock output signal without producing glitches.Type: GrantFiled: January 6, 2016Date of Patent: January 3, 2017Assignee: Rambus Inc.Inventor: Cosmin Iorga
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Patent number: 9485086Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.Type: GrantFiled: October 1, 2015Date of Patent: November 1, 2016Assignee: INPHI CORPORATIONInventors: James L. Gorecki, Jiayun Zhang, Marcial K. Chua, Cosmin Iorga
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Patent number: 9310432Abstract: On-die measurement of power distribution impedance frequency profile of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks resources commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. All measurements are done inside the programmable logic device without the need of external instruments. The measurement method can be used during characterization to select decoupling capacitors or for troubleshooting existing systems, after which the programmable logic device may be reconfigured to perform any other user-defined function.Type: GrantFiled: May 6, 2012Date of Patent: April 12, 2016Inventor: Cosmin Iorga
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Publication number: 20160072620Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.Type: ApplicationFiled: October 1, 2015Publication date: March 10, 2016Inventors: James L. GORECKI, Jiayun ZHANG, Marcial K. CHUA, Cosmin IORGA
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Patent number: 9160345Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.Type: GrantFiled: September 4, 2014Date of Patent: October 13, 2015Assignee: Inphi CorporationInventors: James L. Gorecki, Jiayun Zhang, Marcial K. Chua, Cosmin Iorga
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Publication number: 20130030741Abstract: On-die measurement of power distribution impedance frequency profile of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks resources commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. All measurements are done inside the programmable logic device without the need of external instruments. The measurement method can be used during characterization to select decoupling capacitors or for troubleshooting existing systems, after which the programmable logic device may be reconfigured to perform any other user-defined function.Type: ApplicationFiled: May 6, 2012Publication date: January 31, 2013Inventor: COSMIN IORGA
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Patent number: 7885361Abstract: An embodiment of the present invention provides a system for detecting a phase-shifted signal at high frequencies in data and clock recovery circuitry. An up-pulse generator, in one embodiment, provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal leading the reference signal. A down-pulse generator provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal lagging the reference signal.Type: GrantFiled: December 19, 2005Date of Patent: February 8, 2011Assignee: Teradyne, Inc.Inventor: Cosmin Iorga
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Patent number: 7595746Abstract: A digital-to-analog converter (DAC) includes coarse interpolation DACs configured to produce a current range based on an input digital signal, and fine interpolation DACs configured to produce an output current that is based on an input digital signal and that is within the current range produced by the coarse interpolation DACs.Type: GrantFiled: December 26, 2007Date of Patent: September 29, 2009Assignee: Teradyne, Inc.Inventors: Cosmin Iorga, Alan Hussey