Patents by Inventor Costas Bekas

Costas Bekas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sparse matrix multiplication using a single field programmable gate array module
    Patent number: 10685082
    Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Costas Bekas, Alessandro Curioni, Heiner Giefers, Christoph Hagleitner, Raphael C. Polig, Peter W. J. Staar
  • SPARSE MATRIX MULTIPLICATION USING A SINGLE FIELD PROGRAMMABLE GATE ARRAY MODULE
    Publication number: 20170147531
    Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 25, 2017
    Inventors: Costas Bekas, Alessandro Curioni, Heiner Giefers, Christoph Hagleitner, Raphael C. Polig, Peter W. J. Staar
  • Sparse matrix multiplication using a single field programmable gate array module
    Patent number: 9558156
    Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Costas Bekas, Alessandro Curioni, Heiner Giefers, Christoph Hagleitner, Raphael C. Polig, Peter W. J. Staar