Abstract: A system is disclosed for routing data cells from at least one of a plurality of source port processors to at least one destination port processor. Such a system contemplates each cell comprising a plurality of cell frame portions. In a preferred embodiment of the system of the present invention, each cell generated by the at least one source port processor is separated into its constituent frame portions. Each frame portion has associated therewith a first characteristic and a second characteristic. The cell portions are transmitted to at least one port associated with at least one crossbar chip. The at least one port is in communication with at least two of the plurality of source port processors. Each cell portion is selectively transmitted according to its first characteristic to a corresponding one of the crossbar chips. Each cell portion is selectively transmitted according to its second characteristic to a corresponding one of the ports of the corresponding one of the crossbar chips.

Abstract: A method of facilitating the scheduling of a first multicast request signal of a series of multicast request signals is disclosed, wherein the first request signal is generated to enable the transmission of a multicast data cell by a source port processor to at least one destination port processor. In a preferred embodiment of the invention, the first request signal is received by a roster storage chip associated with a scheduler subsystem. The first request signal has associated therewith a multicast label of a first value and is adapted to schedule transmission of the first multicast cell to the at least one destination port processor at a first time. A roster of the at least one destination port processor to which the first multicast cell is destined is then generated. A dependence distance associated with the first request signal is determined. The dependence distance comprises the numerical value of the difference between a current multicast cell number (CMCN) and a previous multicast cell number (PMCN).

Abstract: A method and system including a short and long term fair shuffling procedure in an arbitration algorithm for a crossbar switch. The shuffling algorithm is deterministic, rather than random, in nature. The shuffling sequence is chosen to ensure a high level of short-term fairness. To ensure long-term fairness, all permutations are eventually used. Both row (input) and column (output) shufflers are used to shuffle priorities of requests. In a preferred embodiment, permuters and shifters are utilized in the shuffler circuits.

Abstract: A packet-switch system utilizes a linecard-to-switch (LCS) protocol to integrate linecards with a switch core. Since the linecards include a majority of the buffering of the system and are located physically away from switch core, the size of the switch core can be reduced in size. The LCS protocol is a label-swapping, credit-based, flow-control, which enables the system to operate without requiring such information as the number of port modules available within a switch core or what Qualities of Service (QoS) or multicast flows are available. In addition, the LCS protocol enables the linecards to contain and manage the majority of the buffers in the system, and also to control the data drop policy within the system.

Abstract: A data packet switch includes a decision tree for classifying data packets, which can be dynamically modified. To conserve memory resources nodes which are found during modification to have matching effects are combined. If only a subset of paths to a node are relevant to a modification, the node is split. Prior to implementation of the modifications, temporary nodes are inserted before modified nodes to preserve existing paths. These temporary nodes are controlled by a single memory value which can be changed to effect all the modifications to the decision tree simultaneously.

Abstract: A hashing method and apparatus uses a hash function that can be modified in real time by a hash control code. The hash function involves the combining together of multiple bit-shifted versions of a multi-bit input to produce a transformed value from which the hash output is formed. The hash control code is used to set the number of input versions used to produce the transformed value and their respective degrees of bit-shifting. The hashing method and apparatus may be used in executing processor branch instructions where the identity of an item to be accessed occupies a search space that varies in size and degree of population between different branch instructions.

Abstract: A data packet switch includes a decision tree for classifying data packets, which can be dynamically modified. To conserve memory resources nodes which are found during modification to have matching effects are combined. If only a subset of paths to a node are relevant to a modification, the node is split. Prior to implementation of the modifications, temporary nodes are inserted before modified nodes to preserve existing paths. These temporary nodes are controlled by a single memory value which can be changed to effect all the modifications to the decision tree simultaneously.

Abstract: A program-controlling processing unit executes instructions stored in memory. A special instruction type is provided for selectively retrieving an element from memory in dependence on the value of input data subject of the instruction. Each instruction of this type has a header identifying the instruction type, and a body in the form of a hash table having at least one entry with both (i) a check value corresponding to a value of interest of the input data subject of the instruction, and (ii) an element to be used when the input data has said value of interest. Upon execution of such an instruction, the related input data is hashed to produce an offset value that is used to access in memory, relative to the position in memory of the current instruction, a corresponding entry in the hash table of the instruction. If a “hit” results (that is, the check value of the accessed entry matches the input data value), the entry element is operatively output.

Abstract: An ATM switch with multicast capability is provided that internally uses input and output identifiers to identify the cell input and output streams, the relevant input identifier being generated for each cell as it arrives. The apparatus has a store for storing both the cell bodies of the cells received by the apparatus and queue data serving to identify in first-in-first-out order, the cell bodies to be output on each output stream. The apparatus is further provided with a send-control subsystem including a scheduling loop and an injection block for injecting output identifiers into the scheduling loop in response to the arrival of new cells. The scheduling loop effects output scheduling of the output streams on the basis of the output identifiers and indicates the next scheduled output stream by outputting the corresponding output identifier, thereby removing it from the scheduling loop.

Abstract: An ATM switch with multicast capability is provided that internally uses input and output identifiers to identify the cell input and output streams, the relevant input identifier being generated for each cell as it arrives. The apparatus stores both the cell bodies of the cells received by the input means and a respective sequence data set for each input stream. Each sequence data set serves to order the cell bodies received for the corresponding input steam in order of receipt. The sequence data sets are held in a queuing block that includes an input control which upon a new cell body being stored, updates the sequence data set of the input stream to which the cell belongs as identified by the corresponding input identifier. The queuing block also has an output control for maintaining for each output stream a sequence position indicator referencing into the sequence data set of the corresponding input stream to indicate the next cell body to be sent on the output stream concerned.

Abstract: A cell switch fabric chip is provided for use in different arrangements of fabric interfacing a cell body memory to N input ports and N output ports. Each port has a plurality of lines over which constituent bits of a cell body can be transferred by a succession of bit shifts. The chip includes M externally-accessible, separate memory buses each with an associated plurality S of shift register blocks. Each shift register block has an input shift register of L elements into which bits can be shifted from an input port line, the input shift register being connected to said input contact to enable bits to be shifted into the register, and an output shift register of L elements out of which bits can be shifted through an output port line. The input shift register can transfer its contents in a parallel transfer onto the associated bus and, similarly, the output shift register can be loaded by a parallel transfer from the bus.

Abstract: A method and arrangement are disclosed for generating a cell-channel identifier ("master VCN") for cells received through at least one input port of an apparatus intended to carry out predetermined functions in respect of these cells. Each cell is, for example, an ATM cell including a channel label that uniquely identifies, for the input port on which the cell is received by the apparatus, a virtual channel with which the cell is associated. In order to provide the master VCN of each cell received, a K-dimensional lookup table storing master VCNs is created. Then for each cell received, a long channel identifier is generated by combining the channel label of the cell with a port label identifying the input port on which the cell was received. Preferably, the long channel identifier is scrambled before being split to provide K keys. Next, these keys are converted into shorter indexes using, for example, simple lookup lists.