Patents by Inventor Costas D. Varmazis

Costas D. Varmazis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure of a pHEMT transistor capable of nanosecond switching
    Patent number: 8174050
    Abstract: A method for fabricating a transistor and the resulting transistor is disclosed. The method generally includes steps (A) to (E). Step (A) may form a high mobility layer. The high mobility layer is generally configured to carry a two-dimensional electron gas. Step (B) may form a planar layer on the high mobility layer. Step (C) may form a barrier layer on the planar layer. Step (D) may form a doped layer on the barrier layer. The doped layer is generally a low bandgap III-V semiconductor. Step (E) may form a gate in contact with the doped layer. The gate may be separated from both a source and a drain by corresponding ungated recess regions. The high mobility layer, the planar layer, the barrier layer, the doped layer, the source, the gate and the drain are generally configured as a pseudomorphic high electron mobility transistor.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: May 8, 2012
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: Timothy E. Boles, Andrew K. Freeston, Costas D. Varmazis
  • STRUCTURE OF A pHEMT TRANSISTOR CAPABLE OF NANOSECOND SWITCHING
    Publication number: 20110147797
    Abstract: A method for fabricating a transistor and the resulting transistor is disclosed. The method generally includes steps (A) to (E). Step (A) may form a high mobility layer. The high mobility layer is generally configured to carry a two-dimensional electron gas. Step (B) may form a planar layer on the high mobility layer. Step (C) may form a barrier layer on the planar layer. Step (D) may form a doped layer on the barrier layer. The doped layer is generally a low bandgap III-V semiconductor. Step (E) may form a gate in contact with the doped layer. The gate may be separated from both a source and a drain by corresponding ungated recess regions. The high mobility layer, the planar layer, the barrier layer, the doped layer, the source, the gate and the drain are generally configured as a pseudomorphic high electron mobility transistor.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Timothy E. Boles, Andrew K. Freeston, Costas D. Varmazis
  • Two layer hermetic-like coating process for on-wafer encapsulation of GaAs MMIC's
    Patent number: 5914508
    Abstract: A microwave system encapsulated by two layers. The first layer is an arylcyclobutene polymer having a thickness greater than the tallest component of the system and only located in predetermined areas. Overlaying the polymer and other preselected areas of the system is a ceramic glass material. These two layers are applied in two layers coating process steps.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: June 22, 1999
    Assignee: The Whitaker Corporation
    Inventors: Costas D. Varmazis, Anthony Kaleta