Abstract: The invention relates to a method for manufacturing an electronic device, particularly a device including a flexible and/or low-cost substrate and/or carbon nanotubes, and also relates to electronic devices produced using said method.

Abstract: Provided is a method for synthesizing carbon agglomerates containing metastable carbyne/carbynoid chains; a method for synthesizing carbon or carbon compound allotropes from the agglomerates containing metastable carbyne/carbynoid chains; and the uses of the methods. The method for synthesizing carbon agglomerates containing metastable carbyne/carbynoid chains includes the following steps: a) forming carbon vapor precursors, containing carbine/carbynoid chains, by decomposing a carbon gas selected from among CH4, C2H2, C2H4, gaseous toluene, and benzene in the form of vapors at a temperature T such that 1 500° C.<T?3 000° C.; and b) condensing the carbon vapor precursors, obtained in Step a), on the surface of a substrate, the temperature Ts of which is less than the temperature T. The invention is particularly of use in the field of electronics.

Abstract: The invention relates to a method for manufacturing an electronic device, particularly a device including a flexible and/or low-cost substrate and/or carbon nanotubes, and also relates to electronic devices produced using said method.

Abstract: The invention includes a controlled graphene film growth process including the production on the surface of a substrate of a layer of a metal having with carbon a phase diagram such that, above a molar concentration threshold ratio CM/CM+CC, where CM is the molar metal concentration in a metal/carbon mixture and CC is the molar carbon concentration in the mixture, a homogeneous solid solution is obtained. The metal layer is exposed to a controlled flux of carbon atoms or carbon-containing radicals or carbon-containing ions at a temperature such that the molar concentration ratio obtained is greater than the threshold ratio to obtain a solid solution of carbon in the metal. The process further includes an operation for modifying the phase of the mixture into two phases, a metal phase and a graphite phase, leading to the formation of at least a lower graphene film at the metal layer incorporating carbon atoms-substrate interface and an upper graphene film at the surface of the metal layer.

Abstract: A process for manufacturing graphene film, comprising the controlled growth of graphene film, comprises the following steps: depositing at least one metal layer on the surface of a substrate; and continuously producing a carbon-rich buried region inside said metal layer by bombarding the metal layer with a flux of carbon atoms and/or carbon ions with an energy higher than about a few tens of electron volts so that they penetrate a portion of the metal layer, allowing said carbon-rich region to be created and maintained, so as to form, by diffusion, through said metal layer, a graphene film at the interface of said metal layer with said substrate.

Abstract: The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13?) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.

Abstract: A method for manufacturing the active plate of a flat matrix display screen, in which each cell comprises an electrode plate connected by a transistor to a first conductive line, comprising the steps of providing an outgrowth coated with an insulator of each first conductive line at the level of each cell; etching or making porous an end portion of each outgrowth; laterally growing, for example, by a VLS method, a PIP or NIN semiconductor structure in each end portion which has been etched or made porous; and establishing a contact at the free end of the semiconductor structure and forming a gate at the level of the median portion of the semiconductor structure.

Abstract: The invention relates to a controlled graphene film growth process characterized in that it comprises the following steps: the production on the surface of a substrate (S1) of a layer of a metal having with carbon a phase diagram such that above a molar concentration threshold ratio CM/CM+CC, where CM is the molar metal concentration in a metal/carbon mixture and CC is the molar carbon concentration in said mixture, a homogeneous solid solution is obtained; the exposure of the metal layer to a controlled flux of carbon atoms or carbon-containing radicals or carbon-containing ions at a temperature such that the molar concentration ratio obtained is greater than the threshold ratio so as to obtain a solid solution of carbon in the metal; and an operation for modifying the phase of the mixture into two phases, a metal phase and a graphite phase respectively, leading to the formation of at least a lower graphene film (31) located at the (metal layer incorporating carbon atoms)/substrate interface and an upper

Abstract: A method for manufacturing the active plate of a flat matrix display screen, in which each cell comprises an electrode plate connected by a transistor to a first conductive line, comprising the steps of providing an outgrowth coated with an insulator of each first conductive line at the level of each cell; etching or making porous an end portion of each outgrowth; laterally growing, for example, by a VLS method, a PIP or NIN semiconductor structure in each end portion which has been etched or made porous; and establishing a contact at the free end of the semiconductor structure and forming a gate at the level of the median portion of the semiconductor structure.

Abstract: The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13?) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.