Abstract: A Universal Serial Bus (USB) split cable is disclosed. In one aspect, the USB split cable provides a USB full-featured Type-C host plug for connecting to a USB Type-C receptacle in a USB host. In another aspect, the USB split cable provides a plurality of USB device plugs for connecting to a plurality of device clients, respectively. The plurality of USB device plugs can be configured individually with different data pin combinations to concurrently support different device clients. By providing the USB split cable, it is possible to support point-to-multipoint USB connection via the plurality of USB device plugs without a USB hub, thus improving mobility of the USB host while reducing costs and power consumption associated with the USB hub.

Abstract: A Universal Serial Bus (USB) split cable is disclosed. In one aspect, the USB split cable provides a USB full-featured Type-C host plug for connecting to a USB Type-C receptacle in a USB host. In another aspect, the USB split cable provides a plurality of USB device plugs for connecting to a plurality of device clients, respectively. The plurality of USB device plugs can be configured individually with different data pin combinations to concurrently support different device clients. By providing the USB split cable, it is possible to support point-to-multipoint USB connection via the plurality of USB device plugs without a USB hub, thus improving mobility of the USB host while reducing costs and power consumption associated with the USB hub.

Abstract: In a portable computing device having a system-on-chip (SoC) Acorn RISC Machine (ARM)-based resource architecture, a peripheral component interconnect express (PCIe) bus is used to insert PCIe device memory into system memory absent a PCIe driver. During a PCIe initialization, the contents of PCIe base address registers (BARs) are mapped or otherwise updated to coincide with values assigned to the PCIe device in the advanced configuration and power interface (ACPI) tables.

Abstract: In a portable computing device having a system-on-chip (SoC) Acorn RISC Machine (ARM)-based resource architecture, a peripheral component interconnect express (PCIe) bus is used to insert PCIe device memory into system memory absent a PCIe driver. During a PCIe initialization, the contents of PCIe base address registers (BARs) are mapped or otherwise updated to coincide with values assigned to the PCIe device in the advanced configuration and power interface (ACPI) tables.

Abstract: System and method for loading and/or updating firmware in a device, e.g., an embedded device, operable to be coupled to a host computer system. A first portion of firmware of the device, e.g., a boot loader, may be executable to operate the device, including processing requests from the host computer system and/or enabling the device to execute a second portion of the firmware, e.g., an operating system for the device. The device may be coupled to other devices or instruments. The second portion of the firmware may allow the host computer system to operate and/or control the other devices or instruments through the device. The host computer system may transmit a different version of the second portion of the firmware to the device, e.g., enabling the device to couple to and operate with a specific instrument. The host computer system may not update the first portion of the firmware.

Abstract: A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to access the data event buffer to process the captured data events without the DMA transfer operation being stopped. In response to the region being filled, the DMA transfer engine may perform the DMA transfer operation to a different region of the data event buffer without the DMA transfer operation being stopped.

Abstract: A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to retrieve captured data events from the data event buffer and to display the retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on the nondeterministic data bus.

Abstract: System and method for loading and/or updating firmware in a device, e.g., an embedded device, operable to be coupled to a host computer system. A first portion of firmware of the device, e.g., a boot loader, may be executable to operate the device, including processing requests from the host computer system and/or enabling the device to execute a second portion of the firmware, e.g., an operating system for the device. The device may be coupled to other devices or instruments. The second portion of the firmware may allow the host computer system to operate and/or control the other devices or instruments through the device. The host computer system may transmit a different version of the second portion of the firmware to the device, e.g., enabling the device to couple to and operate with a specific instrument. The host computer system may not update the first portion of the firmware.

Abstract: A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to access the data event buffer to process the captured data events without the DMA transfer operation being stopped. In response to the region being filled, the DMA transfer engine may perform the DMA transfer operation to a different region of the data event buffer without the DMA transfer operation being stopped.

Abstract: A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to retrieve captured data events from the data event buffer and to display the retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on the nondeterministic data bus.