Abstract: An improved parallel-to-serial-data interface-adaptor that is generally m up of master and slave data processors having master and slave microprocessors, master and slave multibit latches, and separate pairs of read only and random access memories for both the master and slave processors. A data input/output (I/O) bus and an address bus are provided for interconnecting various elements of either the master or slave processors. An interface advantageously interconnects the slave data I/O bus with the master data I/O bus. The master microprocessor advantageously functions to selectively process the master parallel data input when received so that it is compatible with a serial data processor when the selectively processed parallel data input is converted to serial format by a parallel-to-serial-data converter.