Abstract: An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.

Abstract: An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.

Abstract: A vertical cavity surface emitting laser with polarization control includes a first stack of distributed Bragg reflectors positioned on a substrate with an active region including a first cladding region and a second cladding region positioned on opposite sides of an active area overlying the first stack of distributed Bragg reflectors A second stack of distributed Bragg reflectors is positioned on the active region. The second stack has an ion implantation region formed to control and define a lasing threshold of the laser.

Abstract: A semiconductor laser package including a laser chip mounted to a leadframe, and a plastic resin housing for encapsulating the laser chip. The laser chip composed of a vertical cavity surface emitting laser and a photodetector. The vertical cavity surface emitting laser generating an emission along a path. The leadframe being positioned a fixed distance from an emission window formed in the plastic resin housing. The laser chip mounted in precise z-axis alignment from the emission window utilizing the leadframe as a dimensional reference point, with the bump height compensating for variations in laser chip dimension. An optical element is optionally positioned in the path to reflect a portion of the emission.

Abstract: A first stack (112) of distributed Bragg reflectors, a first cladding region (114) disposed on the first stack of distributed Bragg reflectors (112) and including a defect inhibition layer (117) an active area (122) disposed on the first cladding region (114), a second cladding region (132) disposed on the active area (122) and including a defective inhibition layer (136), and a second stack (140) of distributed Bragg reflectors disposed on the second cladding region (132). The defect inhibition layers (117, 136) substantially prevent defects in the active area (122).

Abstract: A substrate having a first surface and a second surface, the first surface having a vertical cavity surface emitting laser disposed therein and second surface having a photodetector integrated disposed therein, wherein the vertical cavity surface emitting laser directs a light signal toward the photodetector.

Abstract: A method of manufacturing a closed cavity LED including forming, on a substrate, a short cavity LED with electrically conductive layers on opposite ends. Depositing a transparent conductive layer of material over one electrically conductive layer and affixing glass or a diamond film over the transparent conductive layer to define and protect a light output area. Removing the substrate and covering the top and sides of the cavity with dielectric material and contact metal. The metal being in contact with the transparent conductive layer and the other electrical contact layer. Thus, a reflector covers the cavity in all directions except the light output area to increase external efficiency.

Abstract: A method of forming a III-V semiconductor device (10, 20) utilizes a III-V semiconductor substrate (11) having a plurality of III-V semiconductor layers (12, 14, 15, 16, 17). A pattern layer ( 19, 24) is formed on the plurality of layers (12, 14, 15, 16, 17). The plurality of III-V semiconductor layers (12, 14, 15, 16, 17) is etched with an isotropic etch that does not etch the pattern layer (19, 24). The isotropic etch undercuts the pattern layer (19, 24) and exposes an area for forming ohmic contacts on the plurality of III-V semiconductor layers. The pattern layer (19, 24) is used as a mask while depositing ohmic contact material (22, 23, 28) onto the area for forming ohmic contacts.

Abstract: An optical semiconductor device is formed by using one controlled etch to form a "T" shaped contact structure on the device (20). The etch rate is controlled by judicious selection of materials to provide a cladding layer (17) that has a predetermined etch rate in hydrofluoric acid, a support layer (10) and a contact layer (18) that are not affected by hydrofluoric acid, a lift-off layer (19) that is dissolved by hydrofluoric acid, and a barrier layer (21). Dissolving of the lift-off layer (19) facilitates removing the barrier layer (21).

Abstract: A monolithic optoelectronic integrated circuit having an optical emission portion (18) and a drive portion (11, or 22 and 21). The drive portion is capable of accepting TTL and standard CMOS logic voltage levels. In a first embodiment, the monolithic optoelectronic integrated circuit (10) has a light emitting diode (18) driven by a dual gate FET (11). In a second embodiment, the monolithic optoelectronic integrated circuit (20) has a light emitting diode (18) driven by two FETs (22 and 21). In each embodiment (10 or 20), a gate (13 or 23) of the respective drive circuit accepts the TTL or standard CMOS logic voltage. Further, in each embodiment current limiting is accomplished by coupling a gate with the source of the FET (11 or 22). Thus, the output of the light emitting diode (18, 18) is controlled by an input signal to the drive circuit.

Abstract: A light emitting diode is provided comprising a substrate which is transparent to the emitted light upon which a plurality of semiconductor layers, including a quantum well active layer, are formed. The materials are chosen not only for their optical characteristics but also so that many of the layers act as etch stops for layers which are formed on top of them. In addition to operational semiconductor layes which form the light emitting diode, two sacrificial semiconductor layers are formed on the substrate which serve as masks during processing and are removed prior to device metallization. An initial pattern is formed in the uppermost semiconductor layer and is transferred down through lower layers using the etch stop layers and selective etches so that further photolithography steps are unnecessary. Electrodes are formed on one side of the device by conventional metal deposition techniques and are self aligned to the LED junction.

Abstract: A high efficiency light emitting diode is achieved through the use of a patterned metal contact. The metal contact is insulated from the structure of the light emitting diode to prevent current flow and subsequent light generation underneath the electrical bond pad. This shifts the drive current out to the patterned portion of the bond pad or metal contact.