Patents by Inventor Craig A. MacKenna

Craig A. MacKenna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8719749
    Abstract: A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 6, 2014
    Assignee: NXP B.V.
    Inventors: Neil E. Birns, Craig A. MacKenna
  • Patent number: 8693614
    Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 8, 2014
    Assignee: NXP B.V.
    Inventors: Craig A. MacKenna, Neil E. Birns
  • Publication number: 20140035648
    Abstract: A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: NXP B.V.
    Inventors: Neil E. Birns, Craig A. MacKenna
  • Publication number: 20120236981
    Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 20, 2012
    Applicant: NXP B.V.
    Inventors: CRAIG A. MACKENNA, NEIL E. BIRNS
  • Patent number: 8229056
    Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 24, 2012
    Assignee: NXP B.V.
    Inventors: Craig A. MacKenna, Neil E. Birns
  • Publication number: 20120155603
    Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: NXP B.V.
    Inventors: CRAIG A. MACKENNA, NEIL E. BIRNS
  • Patent number: 5612634
    Abstract: In an environment where a contact of a mother board is connected to a logic HIGH level voltage through a strong pull-up resistor, and a corresponding contact of an add-in board is connected to an open-drain driver, such that a control line driven by the open-drain driver is provided through the two contacts in normal mode operation when the two contacts make electrical connection, a circuit to sense whether or not the contact of the add-in board is making electrical connection with the contact of the mother board includes a weak pull-down resistor connected at one end to a node connecting the output of the open-drain driver to the contact of the add-in board, and connected at the other end to a ground reference.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: March 18, 1997
    Assignee: Zilog, Inc.
    Inventor: Craig A. MacKenna
  • Patent number: 5495594
    Abstract: By monitoring various combinations of control signals generated by a microprocessor in a computer system in the first operational cycles after it is reset, a peripheral circuit sets itself to respond appropriately to control signals from the microprocessor according to any of several different protocols. For example, an instruction from the microprocessor to write to or read from the peripheral circuit is implemented over two control lines with one of several possible protocols. The circuit determines which protocol is being used each time the system is initialized and thereafter knows when a read or write operation is being performed. Another example is the different wait or acknowledge protocols that various microprocessors use.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: February 27, 1996
    Assignee: Zilog, Inc.
    Inventors: Craig A. MacKenna, Monte J. Dalrymple
  • Patent number: 5319753
    Abstract: A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: June 7, 1994
    Assignee: Zilog, Inc.
    Inventors: Craig A. MacKenna, Hanumanthrao Nimishakavi, Ravi Swami
  • Patent number: 5131081
    Abstract: An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: July 14, 1992
    Assignee: North American Philips Corp., Signetics Div.
    Inventors: Craig A. MacKenna, Cecil H. Kaplinsky
  • Patent number: 4878181
    Abstract: A circuit which expands monochrome character image patterns to color form for use in a raster scanned computer display system. Monochrome patterns are expanded from one bit per pixel to n bits per pixel. Foreground and background colors are programmable in a pattern generator which uses data from the expanded source patterns to select appropriate colors and characters for a destination pattern to be displayed. The expanded multicolor image is generated by hardware.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: October 31, 1989
    Assignee: Signetics Corporation
    Inventors: Craig A. MacKenna, Jan-Kwei J. Li