Patents by Inventor Craig Allan Cavins

Craig Allan Cavins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nanosheet Transistors with Reduced Source/Drain Resistance and Associated Method of Manufacture
    Publication number: 20230290862
    Abstract: A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Applicant: NXP USA, Inc.
    Inventors: Mark Douglas Hall, Craig Allan Cavins, Tushar Praful Merchant, Asanga H. Perera
  • Integrated circuit having a jet vapor deposition silicon nitride film and method of making the same
    Patent number: 5731238
    Abstract: An integrated circuit (10) is formed using jet vapor deposition (JVD) silicon nitride. A non-volatile memory device (11) has a tunnel dielectric layer (27) and an inter-poly dielectric layer (31) that can be formed from JVD silicon nitride. A transistor (12,13,40) is formed that has a gate dielectric material made from JVD silicon nitride. In addition, a passivation layer (47) can be formed overlying a semiconductor device (40) that is formed from JVD silicon nitride.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: March 24, 1998
    Assignee: Motorola Inc.
    Inventors: Craig Allan Cavins, Hsing-Huang Tseng, Ko-Min Chang