Abstract: A pitching mound having a plurality of shell pieces that are releasably connected by a plurality of aligned slots and clips. A stand-alone center shell has a top member supported by a rear vertical support and longitudinally extending braces. A recess for receiving a pitching member is formed in a flat section of the center shell.

Abstract: The faceplate and hanging hook device includes at least one hanging hook integrally formed on a front surface portion of the plate. The plate is mountable to an electrical device securely mounted to a wall-mounted connection box which is securely mounted to a stud of a building. The device serves both as a faceplate for covering the electrical connection box as well as a secure hanging means located at a desirable convenient location in the building.

Abstract: A computer implemented method for generating financial compliance data including generating by a computer system a risk tolerance questionnaire receiving data inputted by a user and stored in a first database on a computer readable medium in communication with the computer system; the risk tolerance questionnaire including data fields representative of a user's financial risk tolerance; generating by the computer system a know-your-client user profile stored in a second database on a computer readable medium in communication with the computer system; and mapping one or more fields from the first database onto one or more fields from the second database, such that the know-your-client user profile is at least partially completed with data obtained from the risk tolerance questionnaire.

Abstract: Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.

Abstract: Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.

Abstract: Examples are provided for a time-interleaved analog-to-digital converter (ADC) with built-in self-healing. The ADC may include multiple ADC slices. Each ADC slice may be configured to operate in one of a normal or a healing mode of operation. In the normal mode of operation, each ADC slice may convert an input analog signal to a single digital output signal in response to a clock signal associated with the ADC slice. In the healing mode of operation, each ADC slice may be operable to convert the input analog signal to two or more digital output signals in response to two or more clock signals. One or more of the digital output signals may replace one or more output signals of failed ADC slices. A first clock signal may be associated with the ADC slice. A second clock signal may be associated with another ADC slice of the plurality of ADC slices.