Abstract: A system and method of demodulating antenna data containing multiple signals in multiple protocols for multiple users is disclosed. The method comprises buffering the antenna data with an input buffer of the demodulation system. Next, the protocol to be demodulated is determined and a dynamically reconfigurable datapath for the system is configured for that protocol. The antenna data containing multiple signals is read from the input buffer, demodulated by the datapath, and stored in an output buffer. The next protocol to be demodulated is determined and the datapath is configured appropriately. Again, the signal for each of the users is demodulated by the datapath and the output data is stored in the output buffer. This process continues until all of the signals for all of the users have been demodulated for all of the prescribed protocols.

Abstract: A reconfigurable chip is described using a reconfigurable functional unit including a shifter unit, arithmetic logic unit and multiplexers. The data path units are interconnected to other data path units. The interconnection is preferably done by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. In a preferred embodiment the reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable functional unit instructions preferably are stored in a reconfigurable functional unit instruction memory which is addressed by a state machine on the chip.

Abstract: A scheduler for a reconfigurable chip is described in which multiple configurations for single function are stored. The scheduler has the option of selecting any one of the configurations. The system increase the efficiency of the reconfiguration chips operation.

Abstract: A method for efficiently updating the coefficients of an adaptive equalizer in the situation of a propagation environment having a dynamically varying multipath. The invention is intended for use in the situation of a static direct path, dynamic multipath, and narrow band signal (bandwidth <<carrier frequency). The method of the present invention is based on the inventor's recognition of the cyclical (rotating) nature of the received signal arising from the effect of small changes in the dynamic multipath delay on a phase term which is part of the received signal. This led the inventor to conclude that the coefficients of the adaptive equalizer would exhibit a similar cyclical behavior. The cyclical behavior of the equalizer coefficients is incorporated into an LMS type coefficient update equation by multiplying the standard coefficient by a "predictive" functional term having a rotational behavior (e.g., e.sup.j.phi.).

Abstract: A semiconductor memory is disclosed having a primary memory array (12) and a dummy column (14) associated therewith that is comprised of a plurality of dummy memory cells (70). The dummy memory cells have a predetermined value stored therein and are sensed with a dummy sense amplifier (18). The dummy sense amplifier (18) has a predetermined offset disposed therein, such that it is in a predetermined state prior to the bit lines separating a sufficient amount to detect the logic state in the dummy memory cell, with an offset disposed therein. This offset prevents the state of the dummy sense amp from being changed until the bit lines are separated by a predetermined value. The primary sense amplifiers associated with the primary memory array (12) are not enabled until the dummy sense amplifier has detected the dummy bit lines as being separating by the predetermined amount.

Abstract: A NOR decode circuit which includes a latch composed of a pair of n-channel transistors and a pair of p-channel transistors with the p-channel transistor of one latch portion coupled to a reference circuit transistor via a first pass transistor and the p-channel transistor of the other latch portion coupled to the address select line controlled transistors via a second pass transistor. The pass transistors are also controlled by an enable row (ENROW) signal. The address transistors are larger and conduct more current than the reference transistor. When ENROW is activated, the n-channel transistors of the latch are enabled and current passes through one side of the latch circuit and through a third transistor in parallel with the address transistors if any of the address transistors are turned on. Current also flows through the other side of the latch circuit and through a fourth transistor in parallel with the reference transistor. The second pass transistor conducts a current I.sub.

Abstract: In quadrature amplitude modulation, circular concentric decision regions capitalize on the observation that when the sample matrix is rotating, it is possible to identify samples more accurately by the radius of their orbit rather than their phase at any given time. The first embodiment provides that a scalar 1.sub.i is calculated for each constellation point so that the constellation point corresponding to the minimum 1.sub.i value is the symbol which the decision device decides was transmitted. The nearest constellation point having the minimum magnitude difference represents the decision. In the second embodiment, two complementary weighting factors are used to provide a weighted average of the two decision criteria in order to make the correct decision. .alpha. is the weight for representing standard rectangular decision regions, while (1-.alpha.) is the weight for representing the circular decision regions. The range for .alpha. is 0<.alpha..ltoreq.1. The variable .alpha.

Abstract: The invention disclosed herein comprises a memory architecture using a new power saving ROW decode implementation. The new power saving ROW decode implementation uses a built in column mux of two. Two ROW drivers are provided for each ROW address. Each row signal from an individual ROW driver connects to every other memory cell (10). An individual ROW driver is selected based on the select signals used in the column mux. Being that the ROW drivers are muxed along with the columns, only memory cells of interest are selected. All unselected memory cell bit lines remain precharged from the previous precharge cycle thus reducing precharge power consumption as compared with previous memory architectures.

Abstract: A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

Abstract: A circuit architecture suitable for use in a television receiver which effectively performs a ghost or echo cancellation procedure on post echo components and pre echo components occurring within the transmission channel. The apparatus features a filter circuit architecture which can be configured under programmed control so as to partition groups of its filter sections to form IIR filters and FIR filters. The filter architecture is suitable for use in multi-circuit configurations and can be used with clustering algorithms to increase the efficiency and optimize the use of the available circuit architecture.

Abstract: A system for improved ghost cancellation for use in particular in television receivers. The system featuring a superior ghost cancellation reference (GCR) signal which exhibits improved performance in noisy environments and which exhibits the flat and wide bandwidth necessary for effective channel characterization which also exhibiting a higher and more evenly distributed amplitude versus time characteristic than that provided by known, non-cyclic ghost cancellation signals. The GCR signal is encoded a selected television line of an eight field sequence of lines however the polarity of the GCR signal is reversed selectively from field to field prior to inserting it in respective television lines. At a decoder or television receiver incorporating the invention, the selected television lines are combined in a manner which provides for both a robust received GCR value and cancellation of the effects of pair-wise constant television line signals on the GCR signals.

Abstract: A circuit architecture suitable for use in a television receiver which effectively performs a ghost or echo cancellation procedure on post echo components and pre echo components occurring within the transmission channel. The apparatus features a filter circuit architecture which can be configured under programmed control so as to partition groups of its filter sections to form IIR filters and FIR filters. The filter architecture is suitable for use in multi-circuit configurations and can be used with clustering algorithms to increase the efficiency and optimize the use of the available circuit architecture.

Abstract: A flip-flop has a master section (74) comprising two transistors (40, 48). The second transistor (48) has two emitters, the second emitter conducting in response to a metastable condition wherein both transistors (40,48) are conducting concurrently, resulting in a metastable output. The second emitter (76) draws additional current through the second transistor (48) after a delay provided by a second clock (78), thus disrupting the equilibrium of the master section (74). By drawing additional current, the second transistor (48) will turn the first transistor (40) off, enabling a valid output.