Patents by Inventor Craig B. Stunkel

Craig B. Stunkel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Priority arbitration mechanism
    Patent number: 7187688
    Abstract: A method is provided for selecting a data source for transmission on one of several logical (virtual) lanes embodied in a single physical connection. Lanes are assigned to either a high priority class or to a low priority class. One of six conditions is employed to determine when re-arbitration of lane priorities is desired. When this occurs a next source for transmission is selected based on a the specification of the maximum number of high priority packets that can be sent after a lower priority transmission has been interrupted. Alternatively, a next source for transmission is selected based on a the specification of the maximum number of high priority packets that can be sent while a lower priority packet is waiting. If initialized correctly, the arbiter keeps all of the packets of a high priority packet contiguous, while allowing lower priority packets to be interrupted by the higher priority packets, but not to the point of starvation of the lower priority packets.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Derrick L. Garmire, Jay R. Herring, Craig B. Stunkel
  • Priority arbitration mechanism
    Publication number: 20040001502
    Abstract: A method is provided for selecting a data source for transmission on one of several logical (virtual) lanes embodied in a single physical connection. Lanes are assigned to either a high priority class or to a low priority class. One of six conditions is employed to determine when re-arbitration of lane priorities is desired. When this occurs a next source for transmission is selected based on a the specification of the maximum number of high priority packets that can be sent after a lower priority transmission has been interrupted. Alternatively, a next source for transmission is selected based on a the specification of the maximum number of high priority packets that can be sent while a lower priority packet is waiting. If initialized correctly, the arbiter keeps all of the packets of a high priority packet contiguous, while allowing lower priority packets to be interrupted by the higher priority packets, but not to the point of starvation of the lower priority packets.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derrick L. Garmire, Jay R. Herring, Craig B. Stunkel
  • Scalable switch wiring technique for large arrays of processors
    Patent number: 5566342
    Abstract: Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of switches called pivot switch sets are used to accomplish this. They are added to the processors and the processor switch sets to form processor clusters. The clusters are each assigned a logical row and column location in an array. Each pivot switch set is connected to all node switch sets in the same assigned column location and to all node switch sets in the same assigned row location as the pivot set. Consequently, any two node switch sets are connected by way of a pivot set located at either (a) the intersection row of the first node set and the column of the second node set or at (b) the intersection of the column of the first node set and the row of the second node set.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Monty M. Denneau, Donald G. Grice, Peter H. Hochschild, Craig B. Stunkel
  • Technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch
    Patent number: 5453978
    Abstract: Apparatus and an accompanying method for establishing deadlock-free routing in a large bi-directional multi-stage inter-connected cross-point based packet switch, particularly, though not exclusively, that employed within a high speed packet network of a massively parallel processing system (400). Specifically, in selecting routes for inclusion within route tables (320, 360, 380) contained within the system, the entire network is effectively partitioned such that certain routes would be prohibited in order to isolate packet traffic that would flow solely between nodes in one partition, e.g. system half (503), of the system from packet traffic that would flow between nodes in the other partition, e.g. another system half (507). In that regard, to pick routes for packets that are to transit between nodes situated in a common partition of the system, those routes that contain a path(s) (524, 544) passing through the other system partition would be prohibited.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: September 26, 1995
    Assignee: International Business Machines Corporation
    Inventors: Harish Sethu, Robert F. Stucke, Craig B. Stunkel
  • Tunable synchronous electronic communication apparatus
    Patent number: 5414832
    Abstract: A synchronous communication apparatus can be tuned to ensure reliable reception of signals propagating along transmission lines. The apparatus can be used as a communication port in a high frequency, highly connected synchronous network in which all ports can be tuned by a single, remote network control device. A local data source outputs a data signal during each of a series of local clock periods. A local source delay circuit receives input data signals from the local data source, and outputs output signals delayed by all amount (mT+.DELTA.pT) relative to corresponding input data signals, where m is a positive integer or zero, and where 0<.DELTA.p<1. The amount of the delay is dependent on the value of a source delay select signal. A local data receiver receives data signals from a local receiver delay circuit. The amount of delay of the local receiver delay circuit is also selectable.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: May 9, 1995
    Assignee: International Business Machines Corporation
    Inventors: Monty M. Denneau, Bruce D. Gavril, Peter H. Hochschild, Craig B. Stunkel
  • Synchronous communication system having multiplexed information transfer and transition phases
    Patent number: 5414740
    Abstract: A communication system segment having phase multiplexing. A first communication station contains a data source which sequentially outputs a series of data signals during a series of clock periods. The data source outputs one data signal from the series during each clock period. The first communication station also contains a transition buffer which has an input connected to the output of the data source. The transition buffer has a first-in, first-out mode in which the transition buffer stores a series of Q data signals output from the data source during the most recent Q clock periods, where Q is an integer greater than zero. A second communication station contains a data receiver which sequentially inputs a series of data signals during a series of clock periods. The data receiver inputs one data signal from the series during each clock period. A communication line connects the output of the data source to the input of the data receiver.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: May 9, 1995
    Assignee: International Business Machines Corporation
    Inventors: Monty M. Denneau, Bruce D. Gavril, Peter H. Hochschild, Craig B. Stunkel
  • Method and apparatus for centralized determination of virtual transmission delays in networks of counter-synchronized communication devices
    Patent number: 5371733
    Abstract: For use by a particular node within a digital data communications network having a plurality of counter-synchronized nodes including the particular node, called the central service node (CSN), and at least one remote node, all nodes being clocked at a common frequency, each node being synchronized by its own nodal time counter and connected to at least one other node by at least one transmission segment that completes a transmission path from the CSN, method and apparatus for: (a) establishing any value of virtual transmission delay (vtd) at individual transmission segments; (b) non-destructively determining the existing vtd at individual transmission segments; and (c) establishing basal distributions of vtd throughout the network and determining the elements thereof, (a), (b), and (c) being achieved without the central service node knowing real transmission delay (rtd) and inter-nodal asynchrony anywhere within the network and without requiring the active participation of any remote node.
    Type: Grant
    Filed: March 4, 1993
    Date of Patent: December 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Monty M. Denneau, Bruce D. Gavril, Peter H. Hochschild, Craig B. Stunkel
  • Communication network with non-unique device identifiers and method of establishing connection paths in such a network
    Patent number: 5371735
    Abstract: A communication network having a service processor, a plurality of terminal nodes, and a network of switch nodes for switchably connecting the service processor to each terminal node by way of one or more connection paths. Each switch node in the communication network is connected to the service processor either directly or through one or more other switch nodes. Each terminal node of the communication network is connected to a switch node. Each switch node and each terminal node has a device identification. At least two nodes have the same device identification. Each target node having the same device identification as another node can preferably be connected to the service processor by way of at least one connection path which does not include any other node having the same device identification as the target node. All switch nodes having the same minimum connection path length may, for example, have the same device identification.
    Type: Grant
    Filed: March 4, 1993
    Date of Patent: December 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Monty M. Denneau, Peter H. Hochschild, Craig B. Stunkel