Patents by Inventor Craig B. Zilles
Craig B. Zilles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9817644Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: GrantFiled: September 28, 2015Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Mauricio Breternitz, Jr., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Patent number: 9146844Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: GrantFiled: May 13, 2013Date of Patent: September 29, 2015Assignee: Intel CorporationInventors: Mauricio Breternitz, Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Publication number: 20130326199Abstract: Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.Type: ApplicationFiled: December 29, 2011Publication date: December 5, 2013Inventors: Grigorios Magklis, Josep M. Codina, Craig B. Zilles, Michael Neilly, Sridhar Samudrala, Alejandro Martinez Vicente, Polychronis Xekalakis, F. Jesus Sanchez, Marc Lupon, Georgios Tournavitis, Enric Gibert Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos E. Kotselidis, Fernando Latorre, Pedro Lopez, Carlos Madriles Gimeno, Pedro Marcuello, Raul Martinez, Daniel Ortega, Demos Pavlou, Kyriakos A. Stavrou
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Publication number: 20130318507Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: ApplicationFiled: May 13, 2013Publication date: November 28, 2013Inventors: Mauricio Breternitz, JR., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Patent number: 8549504Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: GrantFiled: September 25, 2010Date of Patent: October 1, 2013Assignee: Intel CorporationInventors: Mauricio Breternitz, Jr., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Patent number: 8443353Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: GrantFiled: September 25, 2010Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Mauricio Breternitz, Jr., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Publication number: 20120079246Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: ApplicationFiled: September 25, 2010Publication date: March 29, 2012Inventors: Mauricio Breternitz, JR., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Patent number: 7225404Abstract: A method and apparatus for determining forces to be applied to a user through a haptic interface. The method includes the steps of generating a representation of an object in graphic space, sensing the position of the user in real space and calculating a force to be applied to a user in response to the user's haptic interface and the user's fiducial object. The user's fiducial object represents the location in graphic space at which the user's haptic interface would be located if the haptic interface could not penetrate the surfaces of virtual objects.Type: GrantFiled: October 26, 2001Date of Patent: May 29, 2007Assignee: Massachusetts Institute of TechnologyInventors: Craig B. Zilles, J. Kenneth Salisbury, Jr., Thomas H. Massie, David Lawrence Brock, Mandayam A. Srinivasan, Hugh B. Morgenbesser
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Publication number: 20040073905Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.Type: ApplicationFiled: October 7, 2003Publication date: April 15, 2004Inventors: Joel S. Emer, Rebecca L. Stamm, Bruce E. Edwards, Matthew H. Reilly, Craig B. Zilles, Tryggve Fossum, Christopher F. Joerg, James E. Hicks
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Patent number: 6675192Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.Type: GrantFiled: November 11, 2002Date of Patent: January 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Joel S. Emer, Rebecca L. Stamm, Bruce E. Edwards, Matthew H. Reilly, Craig B. Zilles, Tryggve Fossum, Christopher F. Joerg, James E. Hicks, Jr.
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Publication number: 20030105944Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.Type: ApplicationFiled: November 11, 2002Publication date: June 5, 2003Applicant: Hewlett-Packard Development CompanyInventors: Joel S. Emer, Rebecca L. Stamm, Bruce E. Edwards, Matthew H. Reilly, Craig B. Zilles, Tryggve Fossum, Christopher F. Joerg, James E. Hicks
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Patent number: 6493741Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.Type: GrantFiled: October 1, 1999Date of Patent: December 10, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Joel S. Emer, Rebecca L. Stamm, Bruce E. Edwards, Matthew H. Reilly, Craig B. Zilles, Tryggve Fossum, Christopher F. Joerg, James E. Hicks, Jr.
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Patent number: 6369834Abstract: A method and apparatus for determining forces to be applied to a user through a haptic interface. The method includes the steps of generating a representation of an object in graphic space, sensing the position of the user in real space and calculating a force to be applied to a user in response to the user's haptic interface and the user's fiducial object. The user's fiducial object represents the location in graphic space at which the user's haptic interface would be located if the haptic interface could not penetrate the surfaces of virtual objects. In one embodiment, the method calculates a stiffness force to be applied to the user. In other embodiments, the method calculates damping and friction forces to be applied to the user. In one embodiment the step of generating a representation of an object in graphic space includes defining the object as a mesh of planar surfaces and associating surface condition values to each of the nodes defining the planar surfaces.Type: GrantFiled: June 2, 1999Date of Patent: April 9, 2002Assignee: Massachusetts Institute of TechnologyInventors: Craig B. Zilles, J. Kenneth Salisbury, Jr., Thomas H. Massie, David Lawrence Brock, Mandayam A. Srinivasan, Hugh B. Morgenbesser
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Patent number: 6111577Abstract: A method and apparatus for determining forces to be applied to a user through a haptic interface. The method includes the steps of generating a representation of an object in graphic space, sensing the position of the user in real space and calculating a force to be applied to a user in response to the user's haptic interface and the user's fiducial object. The user's fiducial object represents the location in graphic space at which the user's haptic interface would be located if the haptic interface could not penetrate the surfaces of virtual objects. In one embodiment, the method calculates a stiffness force to be applied to the user. In other embodiments, the method calculates damping and friction forces to be applied to the user. In one embodiment the step of generating a representation of an object in graphic space includes defining the object as a mesh of planar surfaces and associating surface condition values to each of the nodes defining the planar surfaces.Type: GrantFiled: April 4, 1996Date of Patent: August 29, 2000Assignee: Massachusetts Institute of TechnologyInventors: Craig B. Zilles, J. Kenneth Salisbury, Jr., Thomas H. Massie, David Lawrence Brock, Mandayam A. Srinivasan, Hugh B. Morgenbesser