Patents by Inventor Craig Barner

Craig Barner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119929
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
  • Publication number: 20200250088
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Craig Barner, David Asher, Richard Kessler, Brad Dobbie, Daniel Dever, Tom Hummel, Isam Akkawi
  • Patent number: 9491099
    Abstract: A method and a system embodying the method for information lookup request processing at a look-aside processor unit entailing storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet is a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a method and a system embodying the method for exception packet processing at a look-aside processor unit entailing storing at least one received lookup transaction request in a first buffer; receiving a packet; determining that the received packet is an exception packet; and associating the exception packet with one of the at least one stored lookup transaction request in accordance with an identifier of the first buffer is disclosed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Cavium, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Steven Craig Barner, Richard Eugene Kessler
  • Publication number: 20150188816
    Abstract: A method and a system embodying the method for information lookup request processing at a look-aside processor unit comprising storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet comprises a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a method and a system embodying the method for exception packet processing at a look-aside processor unit comprising storing at least one received lookup transaction request in a first buffer; receiving a packet; determining that the received packet comprises an exception packet; and associating the exception packet with one of the at least one stored lookup transaction request in accordance with an identifier of the first buffer is disclosed.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: CAVIUM, INC.
    Inventors: Wilson Parkhurst Snyder, II, Steven Craig Barner, Richard Eugene Kessler
  • Patent number: 9065626
    Abstract: In an embodiment, a method includes receiving at a data interface a data stream having a plurality of logical communication channels. The data stream includes in succession a first data burst corresponding to one of the plurality of logical communication channels, a burst control word and a second data burst corresponding to the one or an other of the plurality of logical communication channels. The burst control word includes a first error check that protects the first data burst and the burst control word and a second error check that protects only the burst control word. The first error check and the second error check are examined. Only the one logical communication channel is errored out if the first error check is bad and the second error check is good; all open logical communication channels are errored out if the first error check is bad and the second error check is bad.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: June 23, 2015
    Assignee: Cavium, Inc.
    Inventor: Craig Barner
  • Patent number: 9059836
    Abstract: In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: June 16, 2015
    Assignee: Cavium, Inc.
    Inventor: Craig Barner
  • Publication number: 20150016574
    Abstract: In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 15, 2015
    Inventor: Craig Barner
  • Patent number: 8855248
    Abstract: In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: October 7, 2014
    Assignee: Cavium, Inc.
    Inventor: Craig Barner
  • Patent number: 8544106
    Abstract: Systems and methods are disclosed for enabling access to a protected hardware resource. A hardware component includes at least one protected hardware resource. A unique hardware ID and a unique cryptographically secure or randomly generated enable value (EV) are integrated in the hardware component at the time of manufacturing. At run-time, special software generates or receives from an external source an enable register (ER) value and a comparison is made with the stored enable value. If the ER value and the EV match, access to the protected hardware resource is allowed.
    Type: Grant
    Filed: August 1, 2010
    Date of Patent: September 24, 2013
    Assignee: Cavium, Inc.
    Inventors: Amer Haider, Steven Craig Barner, Richard Eugene Kessler
  • Publication number: 20130101069
    Abstract: In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Cavium, Inc.
    Inventor: Craig Barner
  • Publication number: 20130104012
    Abstract: In an embodiment, a method includes receiving at a data interface a data stream having a plurality of logical communication channels. The data stream includes in succession a first data burst corresponding to one of the plurality of logical communication channels, a burst control word and a second data burst corresponding to the one or an other of the plurality of logical communication channels. The burst control word includes a first error check that protects the first data burst and the burst control word and a second error check that protects only the burst control word. The first error check and the second error check are examined. Only the one logical communication channel is errored out if the first error check is bad and the second error check is good; all open logical communication channels are errored out if the first error check is bad and the second error check is bad.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Cavium, Inc.
    Inventor: Craig Barner
  • Publication number: 20130101076
    Abstract: In an embodiment, a method includes receiving at a data interface a data stream having a first polarity and searching the received data having the first polarity for a unique pattern of a synchronization word within a first quantity of the received data, the synchronization word marking a start of a metaframe having a metaframe length. The polarity of the data stream is reversed to a second polarity if the synchronization word is not found within the first quantity of the received data and the received data having the second polarity is searched for the unique pattern of the synchronization word within a second quantity of the received data.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Cavium, Inc.
    Inventor: Craig Barner
  • Publication number: 20120216050
    Abstract: A microcode authentication unit provides access to a secure hardware unit. A microcode segment is provided to the microcode authentication unit, which generates a signature corresponding to the segment and compares the size and signature of the segment against stored values. If a match is determined, the unit enables access to the secure hardware unit.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 23, 2012
    Applicant: Cavium, Inc.
    Inventors: Craig Barner, David Carlson
  • Publication number: 20120027199
    Abstract: Systems and methods are disclosed for enabling access to a protected hardware resource. A hardware component includes at least one protected hardware resource. A unique hardware ID and a unique cryptographically secure or randomly generated enable value (EV) are integrated in the hardware component at the time of manufacturing. At run-time, special software generates or receives from an external source an enable register (ER) value and a comparison is made with the stored enable value. If the ER value and the EV match, access to the protected hardware resource is allowed.
    Type: Application
    Filed: August 1, 2010
    Publication date: February 2, 2012
    Applicant: CAVIUM NETWORKS
    Inventors: Amer Haider, Steven Craig Barner, Richard Eugene Kessler