Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

Abstract: A method of making an assembly or package comprising 3D blocks may include forming a conductive element horizontally oriented over a first carrier, forming support material around the conductive element, and singulating the conductive element and the support material to form a plurality of 3D blocks. The method may further include rotating each of the plurality of 3D blocks and mounting the plurality of 3D blocks over a second carrier with the conductive traces of the 3D blocks vertically oriented to form a vertically oriented conductive element. A plurality of components may be disposed laterally offset from each of the plurality of 3D blocks, an encapsulant may be disposed thereover s to form a reconstituted panel that may be singulated to form a plurality of individual assemblies.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: The disclosure concerns method of making an interconnect substrate that may comprise providing a core. The core may comprise a composite core, which may comprise a PCB, a laminate core with build-up layers, or molded core. A first patterned frontside conductive layer may be formed over a front side of the core. A first frontside molded dielectric layer may be disposed over the front side of the core and over the first patterned frontside conductive layer. One or more other dielectric layers (such as polyimide) may be disposed before (and under) the first frontside molded dielectric layer. The core may be flipped such that a back side of the core is presented or configured for processing. A first patterned frontside conductive layer may be formed over the back side of the core.

Abstract: An electrical or semiconductor package may comprise an embedded component comprising embedded vertical interconnects (EVIs) extending through a base substrate material from a first surface to a second surface opposite the first surface. An encapsulant may be disposed around and contact four side surfaces of the embedded component. A first electrical interconnect structure comprising a conductive stud may be coupled to a first end of the EVI at the first surface of the embedded component. The encapsulant may contact at least a portion of the side of the conductive stud. A second electrical interconnect structure comprising a portion of a conductive RDL layer may be coupled to a second end of the EVI at the second surface of the embedded component. A component may be coupled to, and mounted over, the first electrical interconnect of the vertical interconnect.

Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: A method of making a semiconductor assembly may include providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around and contacting at least four side surfaces of the semiconductor component and disposed over frontside of the semiconductor component. A first layered structure may be formed as a build-up interconnect structure over the encapsulant and over the semiconductor component. The first layered structure may comprise a first conductive layer formed over the first encapsulant, a first dielectric formed over the first conductive layer, and a second encapsulant disposed over first conductive layer and over first dielectric. An upper surface of the second encapsulant may be planarized to create a flat surface on which to form additional structures, such as a second layered structure or a package interconnect.

Abstract: A method of forming a semiconductor device can comprise providing a first shift region in which to determine a first displacement. A second shift region may be provided in which to determine a second displacement. A unique electrically conductive structure may be formed comprising traces to account for the first displacement and the second displacement. The electrically conductive structure may comprise traces comprising a first portion within the first shift region and a second portion of traces in the second shift region laterally offset from the first portion of traces. A third portion of the traces may be provided in the routing area between the first shift region and the second shift region. A unique variable metal fill may be formed within the fill area. The variable metal fill may be electrically isolated from the unique electrically conductive structure.

Abstract: A method and related structure for a encapsulant defined land grid array (LGA) may comprise a semiconductor chip comprising conductive studs disposed over an active layer of the semiconductor chip, and a first encapsulant disposed around at least a portion of sidewalls of the conductive studs. A surface of the first encapsulant and conductive studs may be planarized. Conductive traces may be disposed over the encapsulant and coupled with the conductive studs. A dielectric layer may be disposed adjacent the conductive traces. LGA pads may be coupled with the conductive traces. A second encapsulant may be disposed over the dielectric layer and the LGA pads. A planar surface may be formed comprising the second encapsulant around the LGA pads and attachment areas on or over the LGA pads. The plurality of attachment areas may be coplanar or recessed the planar surface.

Abstract: A method of making an assembly or package comprising 3D blocks may include forming a conductive element horizontally oriented over a first carrier, forming support material around the conductive element, and singulating the conductive element and the support material to form a plurality of 3D blocks. The method may further include rotating each of the plurality of 3D blocks and mounting the plurality of 3D blocks over a second carrier with the conductive traces of the 3D blocks vertically oriented to form a vertically oriented conductive element. A plurality of components may be disposed laterally offset from each of the plurality of 3D blocks, an encapsulant may be disposed thereover s to form a reconstituted panel that may be singulated to form a plurality of individual assemblies.

Abstract: The disclosure concerns methods of forming a semiconductor device with a repairable redistribution layer (RDL) design, comprising: preparing an original repairable RDL design; forming first conductive segments of the repairable RDL design; inspecting the first conductive segments of the repairable RDL design to detect manufacturing defects; detecting at least one defect in the first conductive segments; and forming second conductive segments of the repairable RDL design according to a new custom RDL design to mitigate the negative effects of the at least one defect among the first conductive segments. The disclosure also concerns semiconductor devices with a repairable RDL design.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: The disclosure concerns methods of forming a semiconductor device with a repairable redistribution layer (RDL) design, comprising: preparing an original repairable RDL design; forming first conductive segments of the repairable RDL design; inspecting the first conductive segments of the repairable RDL design to detect manufacturing defects; detecting at least one defect in the first conductive segments; and forming second conductive segments of the repairable RDL design according to a new custom RDL design to mitigate the negative effects of the at least one defect among the first conductive segments. The disclosure also concerns semiconductor devices with a repairable RDL design.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A method of forming a semiconductor device can comprise providing a first shift region in which to determine a first displacement. A second shift region may be provided in which to determine a second displacement. A unique electrically conductive structure may be formed comprising traces to account for the first displacement and the second displacement. The electrically conductive structure may comprise traces comprising a first portion within the first shift region and a second portion of traces in the second shift region laterally offset from the first portion of traces. A third portion of the traces may be provided in the routing area between the first shift region and the second shift region. A unique variable metal fill may be formed within the fill area. The variable metal fill may be electrically isolated from the unique electrically conductive structure.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 ?m-20 ?m.