Abstract: The present disclosure is directed to a system and method for monitoring drive health. A method for monitoring drive health may comprise: a) conducting a predictive fault analysis for at least one drive of a RAID; and b) copying data from the at least one drive of the RAID to a replacement drive according to the predictive fault analysis. A system for monitoring drive health may comprise: a) means for conducting a predictive fault analysis for at least one drive of a RAID; and b) means for copying data from the at least one drive of the RAID to a replacement drive according to the predictive fault analysis.

Abstract: The present disclosure is directed to a system and method for monitoring drive health. A method for monitoring drive health may comprise: a) conducting a predictive fault analysis for at least one drive of a RAID; and b) copying data from the at least one drive of the RAID to a replacement drive according to the predictive fault analysis. A system for monitoring drive health may comprise: a) means for conducting a predictive fault analysis for at least one drive of a RAID; and b) means for copying data from the at least one drive of the RAID to a replacement drive according to the predictive fault analysis.

Abstract: Disclosed is a system and method for using a mirrored disk as a bootable backup disk for a computer system. A mirroring routine may be used to create a backup disk, then discontinued during normal operations. Should a problem occur with the main disk, the computer system may be rebooted using the backup disk and the main disk can be rebuilt from the backup disk using the mirroring routine. The system and method may be applied to two disk systems and various multiple-disk arrays such as RAID systems.

Abstract: The present invention is directed to a parallel/serial SCSI with legacy support. A small computer system interface (SCSI) converter module may include a small computer system interface (SCSI) converter. The converter is suitable for converting a parallel bus structure to a serial bus structure, and the converter is also suitable for supporting a parallel bus structure to a parallel bus structure.

Abstract: Disclosed is a system and method for using a mirrored disk as a bootable backup disk for a computer system. A mirroring routine may be used to create a backup disk, then discontinued during normal operations. Should a problem occur with the main disk, the computer system may be rebooted using the backup disk and the main disk can be rebuilt from the backup disk using the mirroring routine. The system and method may be applied to two disk systems and various multiple-disk arrays such as RAID systems.

Abstract: The present invention is directed to a simple and scalable RAID XOR assist logic with overlapped operations. An apparatus suitable for performing overlapped operations may include an exclusive OR (XOR) unit suitable for performing an exclusive OR (XOR) operation. A memory communicatively coupled to the XOR unit, wherein the memory is suitable for storing a first item of data and a second item of data thereby enabling overlapped operations of the exclusive OR (XOR) unit.

Abstract: An apparatus for mounting a heat sink to a chip package such as a BGA type chip package or the like is disclosed. In an exemplary embodiment, ground bumps are formed on the die substrate of the chip package and on the heat mating surface of the heat sink to be attached to the package. The ground bumps formed on the die protrude into the body of dimples formed in the body of the chip encapsulation package to make thermal/electrical ground contact with the ground bumps formed on the heat mating surface of the heat sink for electrically grounding the heat sink.

Abstract: A method and apparatus for generating an interrupt signal. A counter value is decremented each time a task is completed by a slave processor. The counter value is incremented each time a task is read by the slave processor. A delay value is set using the counter value. An interrupt is generated after a period of time set by the delay value has passed. The counter value is compared to a threshold value. The interrupt is generated upon detecting a condition in which the counter value is less than the threshold value or when the completion queue is full instead of after the period of time.

Abstract: In a computer system having a peripheral bus and a peripheral device coupled together, a method for testing data transfer integrity of the peripheral bus includes the step of transferring first data to the peripheral device via the peripheral bus. Another step of the method includes generating a first error signal if the first data was corrupted during the first data transferring step. The method also includes updating a counter in response to generation of the first error signal. The method further includes generating a second error signal if the counter exceeds a predetermined threshold. Moreover, the method includes the steps of transferring the first data in a first manner, and in response to generation of the second error signal, transferring second data to the peripheral device in a second manner that is different than the first manner. The difference between the first manner and the second manner may include a difference in transfer rate and/or a difference in bus width.

Abstract: Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU.

Abstract: A method and apparatus for a method for measuring performance of an I/O bus. The method includes the steps of (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a). One embodiment of the apparatus includes a mechanism for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter. Another embodiment of the apparatus includes a mechanism for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter.

Abstract: Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU.

Abstract: An interrupt signal indicating the existence of a bus configuration error within a disk array system is generated by monitoring the enable signals controlling bus drivers included in the array system. The array configuration error detector includes bus configuration error detection logic for each multiple-source bus within the array. Each bus configuration error detector is connected to receive all enable signals for the bus drivers associated with one bus and decode the received enable signals to generate an error signal when more than one of the received enable signals is active. The error signals generated for each of the multiple-source busses are provided to an adder and combined to form the configuration error interrupt signal for the array.

Abstract: A simple method and circuit for qualifying and combining individual request signals received from a plurality of disk drives within a disk array to generate a single, synchronized request signal for the disk array. The circuit includes an activity register for storing a bit pattern which identifies those disk drives which are in use within the array. Each bit position within the activity corresponds to a different disk drive within the disk array. A logic one stored in a bit position identifies the disk drive corresponding to the bit position as being active while a logic zero stored in a bit position identifies the disk drive corresponding to the bit position as being inactive.

Abstract: A disk array controller including a data path architecture which can be configured to perform data transfer operations between a host system and a plurality of disk drives configured as a RAID level 1, 3, 4 of 5 disk array. The data path architecture includes a plurality of array channels for coupling selected disk drives with a host system bus and circuitry for generating parity information during write operations. Each array channel includes a data bus connected through bus drivers to the host bus, its associated disk drive, and the input and output of the parity generation circuitry. The bus drivers control the placement of data unto the array busses and the direction of the data flow on the array busses.

Abstract: An array controller including a novel data path structure for effecting data transfers between a host computer system bus and four array busses associated with a RAID level 3 disk array without the utilization of a buffer between the host system and the array. The data path structure includes a host register associated with each array bus, each host register being connected to the host bus for receiving data therefrom; a first array register associated with each array bus, each first array register being connected to a corresponding host register for receiving data therefrom and connected to its associated array bus for providing data thereto; and a second array register associated with each array bus, each second array register being connected to it associated array bus for receiving data therefrom and connected to the host bus for providing data thereto.

Abstract: An interrupt signal for a disk array is generated by selectively combining interrupt signals received from the individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the array interrupt signal includes logic for combining a first group of selected interrupt signals to generate a group interrupt signal having a HIGH state when each one of the signals in the first group is at a HIGH state, and logic which combines a second group of selected interrupt signals to generate an independent interrupt signal having a HIGH state when any one of the interrupt signals of the second group is at a HIGH state. The group and independent interrupt signals are gated together through use of an OR gate to generate the disk array interrupt signal. The logic for generating the group and independent interrupt signals can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user.

Abstract: A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse.

Abstract: A flip-flop including a master section having an input for receiving a data signal and a pair of outputs, one output for providing the data signal state, and one output for providing the data signal state complement, and a slave section having a pair of inputs, one connected to each of the outputs of the master section, and a pair of outputs, one of the outputs of the slave section for providing the data signal state, and one of the outputs of the slave section for providing the data signal state complement. A cross coupling circuit is provided in the slave section for connecting the slave section input for receiving the data signal state to the slave section output for providing the data signal state, and for connecting the slave section input for receiving the data signal state complement to the slave section output for providing the data signal state complement.