Abstract: Various arrangements for allocating spectrum between a cellular network provider and a secondary operator are presented. A cellular network component of the secondary operator may determine that spectrum at a secondary operator radio unit (RU) is not currently needed. The cellular network component of the secondary operator may cause the spectrum to be released for use by a cellular network operator such that the secondary operator RU is not permitted to use the released spectrum. A cellular network operator RU may then communicate with a first set of user equipment (UE) using the released spectrum. The secondary operator RU and cellular network operator RU may be located at a same location.

Abstract: An electronic device includes a drift region having a first conductivity type and a grid including a plurality of doped regions formed in the drift region and having a second conductivity type. The doped regions have a dopant concentration greater than 2.2×1019 cm?3. Related methods are also disclosed.

Abstract: Semiconductor devices include a semiconductor layer structure having a wide band-gap semiconductor drift region having a first conductivity type. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having first and second opposed sidewalls that extend in a first direction in the upper portion of the semiconductor layer structure. These devices further include a deep shielding pattern having a second conductivity type that is opposite the first conductivity type in the semiconductor layer structure underneath a bottom surface of the gate trench, and a deep shielding connection pattern that has the second conductivity type in the first sidewall of the gate trench. The devices include a semiconductor channel region that has the first conductivity type in the second sidewall of the gate trench.

Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.

Abstract: A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <0001> direction of less than 8°.

Abstract: A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <0001> direction of less than 8°.

Abstract: A bipolar junction transistor (BJT) includes a silicon carbide (SiC) collector layer of first conductivity type, an epitaxial silicon carbide base layer of second conductivity type on the silicon carbide collector layer, and an epitaxial silicon carbide emitter mesa of the first conductivity type on the epitaxial silicon carbide base layer. An epitaxial silicon carbide passivation layer of the first conductivity type is provided on at least a portion of the epitaxial silicon carbide base layer outside the silicon carbide emitter mesa. The epitaxial silicon carbide passivation layer can be configured to fully deplete at zero device bias. Related fabrication methods also are disclosed.

Abstract: A silicon carbide device is fabricated by forming a plurality of a same type of silicon carbide devices on at least a portion of a silicon carbide wafer in a predefined pattern. The silicon carbide devices have corresponding first contacts on a first face of the silicon carbide wafer. The plurality of silicon carbide devices are electrically, tested to identify ones of the plurality of silicon carbide devices which pass an electrical test. The first contact of the identified ones of the silicon carbide devices are then selectively interconnected. Devices having a plurality of selectively connected silicon carbide devices of the same type are also provided.