Patents by Inventor Craig Child
Craig Child has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11417525Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.Type: GrantFiled: October 8, 2018Date of Patent: August 16, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Martin O'Toole, Keith Donegan, Brendan O'Brien, Hsueh-Chung Chen, Terry A. Spooner, Craig Child, Sean Reidy, Ravi Prakash Srivastava, Louis Lanzerotti, Atsushi Ogino
-
Publication number: 20200111668Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventors: Martin O'Toole, Keith Donegan, Brendan O'Brien, Hsueh-Chung Chen, Terry A. Spooner, Craig Child, Sean Reidy, Ravi Prakash Srivastava, Louis Lanzerotti, Atsushi Ogino
-
Patent number: 10566231Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.Type: GrantFiled: April 30, 2018Date of Patent: February 18, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan
-
Publication number: 20190333805Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan
-
Patent number: 9691971Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.Type: GrantFiled: June 24, 2015Date of Patent: June 27, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Seowoo Nam, Ming He, Craig Child, Hyun-Jin Cho
-
Publication number: 20160372413Abstract: One method includes, among other things, forming a bi-layer etch stop layer above a conductive contact comprised of titanium nitride, the bi-layer etch stop layer consisting of an upper second layer that is made of aluminum nitride, forming a patterned etch mask comprised of a layer of titanium nitride above a second layer of insulating material, with the bi-layer etch stop layer in position above the conductive contact, performing an etching process through the patterned etch mask to define a cavity in the second layer of insulating material, performing a second etching process to remove at least the layer of titanium nitride of the patterned etch mask, forming an opening in the bi-layer etch stop layer so as to thereby expose a portion of the conductive contact and forming a conductive structure in the cavity that is conductively coupled to the exposed portion of the conductive contact.Type: ApplicationFiled: June 17, 2015Publication date: December 22, 2016Inventors: Anbu Selvam Mahalingam, Ashwini Chandrashekar, Craig Child
-
Patent number: 9431294Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.Type: GrantFiled: October 28, 2014Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Ming He, Errol Todd Ryan, Roderick Alan Augur, Craig Child, Larry Zhao
-
Publication number: 20160190207Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.Type: ApplicationFiled: June 24, 2015Publication date: June 30, 2016Inventors: Seowoo Nam, Ming He, Craig Child, Hyun-Jin Cho
-
Publication number: 20160118292Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.Type: ApplicationFiled: October 28, 2014Publication date: April 28, 2016Inventors: Ming He, Errol Todd Ryan, Roderick Alan Augur, Craig Child, Larry Zhao
-
Patent number: 9165770Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.Type: GrantFiled: September 26, 2013Date of Patent: October 20, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Ming He, Seowoo Nam, Craig Child
-
Publication number: 20150087149Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: Globalfoundries, Inc.Inventors: Ming He, Seowoo Nam, Craig Child
-
Patent number: 8822342Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.Type: GrantFiled: December 30, 2010Date of Patent: September 2, 2014Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Craig Child, Muhammed Shafi Kurikka Valappil Pallachalil, Habib Hichri, Matthew Angyal, Hideshi Miyajima
-
Patent number: 8513109Abstract: A method of manufacturing an interconnect structure for a semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.Type: GrantFiled: March 21, 2011Date of Patent: August 20, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventor: Craig Child
-
Publication number: 20120168957Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., ADVANCED MICRO DEVICES CORPORATIONInventors: Ravi Prakash SRIVASTAVA, Oluwafemi O. OGUNSOLA, Craig CHILD, Muhammed Shafi Kurikka Valappil PALLACHALIL, Habib HICHRI, Matthew ANGYAL, Hideshi MIYAJIMA
-
Publication number: 20110171822Abstract: A method of manufacturing an interconnect structure for a semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.Type: ApplicationFiled: March 21, 2011Publication date: July 14, 2011Applicant: GLOBALFOUNDRIES INC.Inventor: Craig CHILD
-
Patent number: 7932613Abstract: A semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate, and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.Type: GrantFiled: March 27, 2009Date of Patent: April 26, 2011Assignee: GlobalFoundries Inc.Inventor: Craig Child
-
Publication number: 20100244267Abstract: A semiconductor device having a device substrate is provided. The semiconductor device comprises an electrically-conductive pad formed overlying the device substrate, an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity, the electrically-conductive platform having a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion, and a cushioning material disposed in the cavity.Type: ApplicationFiled: March 27, 2009Publication date: September 30, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventor: Craig CHILD
-
Publication number: 20080060577Abstract: A paint shield for a mounting bracket comprising a member having a front side, a back side, and at least one edge and at least one level disposed on the member. There can be a horizontal and a vertical level disposed on the paint shield.Type: ApplicationFiled: November 1, 2006Publication date: March 13, 2008Inventors: Ray Call, Olivier Hennessy, Scott Struthers, Craig Childs