Abstract: Systems and methods for authenticating an applicant. In one implementation, the applicant indicates to an acquirer an existing account for which the applicant wishes to be authenticated. The acquirer sends a message over an electronic funds transfer (EFT) network to an issuer of the account requesting a set of questions to ask the applicant. The issuer replies with a set of questions. The acquirer asks the applicant the questions, and forwards the applicant's answers to the issuer. The issuer compares the answers with known information relating to the account and decides, based on the comparison, whether the applicant is authenticated. The issuer then communicates its decision to the acquirer. Preferably, the messages and their associated replies are added to the set of messages handled by the EFT network, so that authentication may be handled in a standardized way without proliferating applicants' secret information.

Abstract: Systems and methods for authenticating an applicant. In one implementation, the applicant indicates to an acquirer an existing account for which the applicant wishes to be authenticated. The acquirer sends a message over an electronic funds transfer (EFT) network to an issuer of the account requesting a set of questions to ask the applicant. The issuer replies with a set of questions. The acquirer asks the applicant the questions, and forwards the applicant's answers to the issuer. The issuer compares the answers with known information relating to the account and decides, based on the comparison, whether the applicant is authenticated. The issuer then communicates its decision to the acquirer. Preferably, the messages and their associated replies are added to the set of messages handled by the EFT network, so that authentication may be handled in a standardized way without proliferating applicants' secret information.

Abstract: Trigger reception on different instrumentation devices may be synchronized by each instrumentation device generating one or more trigger enable signals and delaying performance of an operation in response to a trigger signal until a transition in a trigger enable signal. An instrumentation system may include several instrumentation devices and a communication medium coupling the instrumentation devices. One of the instrumentation devices may process data in response to a sample clock signal. That instrumentation device may also generate a trigger enable signal and delay performing an operation in response to a trigger signal transmitted via the communication medium until a transition in the trigger enable signal occurs. The trigger enable signal is not the sample clock signal. The trigger enable signal may be synchronized to another trigger enable signal generated by another one of the instrumentation devices.

Abstract: System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common reference. Each device is configured to transmit respective signals to the STM within a common clock cycle. Respective delays corresponding to the devices are determined based on the respective transmission times, where the respective delays are applicable to respective signals received from the devices to synchronize received corresponding pulses in the signals to within a common clock cycle. The respective delays are applied to respective signals received from the plurality of devices to synchronize received corresponding pulses in the signals to within the common clock cycle, after which the STM is operable to trigger the devices as a single device.

Abstract: A system and method for efficiently detecting and correcting transmission errors in packet-based communications by using cumulative error detection codes. The system may comprise a transmitting unit, which transmits one or more data packets. Each of the transmitted packets may comprise a plurality of transmission subunits. The transmitting unit preferably generates a cumulative error detection code (e.g., cumulative CRC code) for each of the transmission subunits of a packet. The system may further comprise a receiving unit to receive each of the transmission subunits of the packet. The receiving unit preferably generates a new cumulative error detection code for each of the received transmission subunits. The new cumulative error detection code is compared to the received cumulative error detection code to determine if any errors occurred in the transmission of the transmission subunit.

Abstract: In some embodiments, a user may select an elemental function such as read, write, or configuration from a graphical programming environment. A file may be created that instantiates functionality into a programmable hardware element to allow it to send a command across a serial protocol to peripheral interface circuitry and ultimately to peripheral chips (e.g., network chips on a CAN). The elemental node concept may be generic to any network chip because the node may contain only the general data of a packet (e.g., command type, value of data bytes, etc). The actual interface to a network chip may be handled inside the peripheral interface circuitry. The peripheral interface circuitry may have the details of the network chip in which it interfaces and may abstract details of the network chip from the target programmable hardware element through the serial protocol.

Abstract: In one embodiment, a system comprises a delay determining unit that may be operable to determine a relative delay between the first signal provided by the first source and the second signal provided by the second source, based upon a travel path of the first signal and a travel path of the second signal. In addition, a delay circuit, comprised within the waveform generator, may be configured to be programmed to delay output of the first signal to output the first signal at a predetermined position with respect to output of the second signal, based on the determined relative delay. More specifically, in one embodiment, the delay circuit may be configured to be automatically programmed to add the relative delay to the output of the first signal to automatically align the output of the first signal with respect to the output of the second signal.