Abstract: Means and structure for encoding binary data ensures that, on average, the encoded data provides a balanced data stream having an equal number of logical one and logical zero bits. An indicator bit of known value is appended to N data bits, forming a group of N+1 bits. The polarity of this group is determined, i.e. whether the group contains more ones than zeros. The cumulative polarity of all bits sent over the communication link is also maintained. When the polarity of the group is the same as the cumulative polarity, all bits in the group are inverted and the inverted group is transmitted. Otherwise the bits in the group are transmitted in their original form. To decode the transmitted bits, the bit stream is framed to separate each series of N+1 bits. The value of the indicator bit on the receiver side of the communication link indicates whether the group has been inverted. If the group has been inverted, it is reinverted on the receiver side of the link to provide the N data bits in their original form.

Abstract: A family of Phase Locked Loop circuits and methods for extraction of a clock signal from a digital data stream, for example as received by a data communication link receiver is taught. The circuits of this invention are particularly advantageous in gigabit rate links where the propagation delay of digital circuits is comparable to the duration of a bit time interval and therefore careful matching of clock extracting and data sampling circuit topology is required. In certain embodiments, a frequency detector is included making the structure suitable for use in situations where there is a large fractional difference between the incoming data rate and the free running frequency of the receiver VCO. Such is the case when both the incoming data rate and the receiver VCO frequency are not controlled by a precision element such as a crystal or a Surface Acoustic Wave device.