Patents by Inventor Craig D. Eaton

Craig D. Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Avoiding BIST and MBIST intrusion logic in critical timing paths
    Patent number: 8990623
    Abstract: Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Craig D. Eaton, Ganesh Venkataramanan, Srikanth Arekapudi
  • AVOIDING BIST AND MBIST INTRUSION LOGIC IN CRITICAL TIMING PATHS
    Publication number: 20120124435
    Abstract: Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Craig D. Eaton, Ganesh Venkataramanan, Srikanth Arekapudi
  • Method and apparatus for clock cycle stealing
    Patent number: 7913103
    Abstract: A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 22, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Spencer M. Gold, Bill K. C. Kwan, Craig D. Eaton
  • METHOD AND APPARATUS FOR CLOCK CYCLE STEALING
    Publication number: 20090063888
    Abstract: A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Inventors: Spencer M. Gold, Bill K.C. Kwan, Craig D. Eaton